| commit | 0cf2f9686a98781ecde8d43bb030caefb3200a6c | [log] [tgz] |
|---|---|---|
| author | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Fri Mar 18 01:24:19 2022 +0000 |
| committer | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Fri Mar 18 01:24:19 2022 +0000 |
| tree | aed714958ba43fccbc8c7e2976b33299a475c534 | |
| parent | b1f30843cb0e1f9ceaef32d5071a386853debcc2 [diff] |
updated power pins
Demonstration of the fully open FABulous eFPGA using the OpenLane flow.
This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.
Refer to README for this sample project documentation.