commit | b1f30843cb0e1f9ceaef32d5071a386853debcc2 | [log] [tgz] |
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author | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Fri Mar 18 00:38:20 2022 +0000 |
committer | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Fri Mar 18 00:38:20 2022 +0000 |
tree | 1fa105260e6de6034acbc0241ac11c9f58e4a51e | |
parent | f277036790028f5f9c61e1261d1f1e0c0828a275 [diff] |
updated license info
Demonstration of the fully open FABulous eFPGA using the OpenLane flow.
This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.
Refer to README for this sample project documentation.