| commit | 1f28d8103ca78feabf0947fdb17966ce90a2829a | [log] [tgz] |
|---|---|---|
| author | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Mon Mar 21 21:55:30 2022 +0000 |
| committer | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Mon Mar 21 21:55:30 2022 +0000 |
| tree | cb13fe37a2613a14bc930c0c1ba26c680cbbabab | |
| parent | 603d248573ac34a878dda2b240233a9be2dd0d42 [diff] |
added PDN
Demonstration of the fully open FABulous eFPGA using the OpenLane flow.
This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.
Refer to README for this sample project documentation.