| commit | 603d248573ac34a878dda2b240233a9be2dd0d42 | [log] [tgz] |
|---|---|---|
| author | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Mon Mar 21 20:54:22 2022 +0000 |
| committer | nguyendao-uom <nguyen.dao@manchester.ac.uk> | Mon Mar 21 20:54:22 2022 +0000 |
| tree | 54f247159d55014e22feb4e99a5150650719c615 | |
| parent | 0cf2f9686a98781ecde8d43bb030caefb3200a6c [diff] |
updated decap_12
Demonstration of the fully open FABulous eFPGA using the OpenLane flow.
This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.
Refer to README for this sample project documentation.