Completed check-in 3 with QSPI
11 files changed
tree: 427cffbb3cc1d9956bd1d78d04fcd43e98b73cd7
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. sdc/
  10. sdf/
  11. signoff/
  12. spef/
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  14. verilog/
  15. .gitignore
  16. LICENSE
  17. Makefile
  18. README.md
README.md

Azadi-III

License UPRJ_CI Caravel Build

Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, QSPI and timer.