commit	1c86ab2c32baca2a919402bd82a68044ca610f28	[log] [tgz]
author	Rameen Anwar <ramianwer1996@gmail.com>	Mon Mar 21 21:48:35 2022 -0700
committer	Rameen Anwar <ramianwer1996@gmail.com>	Mon Mar 21 21:48:35 2022 -0700
tree	427cffbb3cc1d9956bd1d78d04fcd43e98b73cd7
parent	5b92b436c5af98395b6d31b2bf7e1ba2e6d10b38 [diff]

Completed check-in 3 with QSPI

11 files changed

tree: 427cffbb3cc1d9956bd1d78d04fcd43e98b73cd7

.github/
def/
docs/
gds/
lef/
mag/
maglef/
openlane/
sdc/
sdf/
signoff/
spef/
spi/
verilog/
.gitignore
LICENSE
Makefile
README.md

README.md

Azadi-III

Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it “buraq”, it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, QSPI and timer.