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  1. dcf7aef final gds oasis by Jeff DiCorpo · 6 days ago main
  2. e6b01ce Update user_defines.v by Priyanshu5437 · 6 weeks ago
  3. d2b12fe Update user_proj_example.v by Priyanshu5437 · 6 weeks ago
  4. 3d8ee9c Update README.md by Priyanshu5437 · 6 weeks ago
  5. 70e0d4f Update README.md by Priyanshu5437 · 6 weeks ago

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note

Please fill in your project documentation in this README.md file

This project simulates the design of a paralle in parallel out shift register using verilog HDL. A parallel in parallel out shift register works in a similar way as a parallel in serial out shift register. The only difference is that the output is taken parallely instead of serially. Thats why the name given as parallel in parallel out shift register.In this design, four D-Flip-flops are used with clock and input signals.