Clone this repo:


  1. 811d9db final gds oasis by Jeff DiCorpo · 1 year, 6 months ago main
  2. c9f8362 action: update build by roman3017 · 1 year, 7 months ago
  3. b8c3d42 make prescale localparam by roman3017 · 1 year, 7 months ago
  4. 9159812 move user pins from 33:37 to 16:20 by roman3017 · 1 year, 7 months ago
  5. 1a29b29 action: update build by roman3017 · 1 year, 7 months ago

MPW shuttle


Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.

See verilog/rtl/fpga folder for FPGA tests.

mkdir -p dependencies
export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src
export PDK_ROOT=$(pwd)/dependencies/pdks
export PDK=sky130A
make setup

make user_proj_example
klayout -l dependencies/pdks/sky130A/ gds/user_proj_example.gds

make user_project_wrapper
klayout -l dependencies/pdks/sky130A/ gds/user_project_wrapper.gds

make verify-usb2uart-rtl
make verify-usb2uart-gl

#make extract-parasitics
make create-spef-mapping
#make caravel-sta

rm -rf ~/mpw_precheck/
make precheck
make run-precheck
#make compress


  • MPW-8 Shuttle projects (project 1758)
  • USB IP taken from ulixxe
  • UART IP taken from alexforencich
  • Harness Harness specification
  • OpenLane OpenLane documentation
  • Board Test board
  • PLL PLL registers calculator
  • QSG Quick start guide
  • README A sample project documentation