commit | b8c3d42f2ea76f0579d2c11349e28c011b9967ea | [log] [tgz] |
---|---|---|
author | roman3017 <rbacik@hotmail.com> | Sat Dec 31 18:43:23 2022 -0800 |
committer | roman3017 <rbacik@hotmail.com> | Sat Dec 31 18:43:23 2022 -0800 |
tree | f7679c46f10d55511109dc575ad789a1779d3ef7 | |
parent | 9159812fac58a83c26f3b57f93e05a17544def99 [diff] |
make prescale localparam
Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.
See verilog/rtl/fpga folder for FPGA tests.
mkdir -p dependencies export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src export PDK_ROOT=$(pwd)/dependencies/pdks export PDK=sky130A make setup make user_proj_example klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_proj_example.gds make user_project_wrapper klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds make verify-usb2uart-rtl make verify-usb2uart-gl #make extract-parasitics make create-spef-mapping #make caravel-sta rm -rf ~/mpw_precheck/ make precheck make run-precheck #make compress