commit b8c3d42f2ea76f0579d2c11349e28c011b9967ea
author roman3017 <rbacik@hotmail.com> Sat Dec 31 18:43:23 2022 -0800
committer roman3017 <rbacik@hotmail.com> Sat Dec 31 18:43:23 2022 -0800
tree f7679c46f10d55511109dc575ad789a1779d3ef7
parent 9159812fac58a83c26f3b57f93e05a17544def99

make prescale localparam

verilog/rtl/usb2uart.v

diff --git a/verilog/rtl/usb2uart.v b/verilog/rtl/usb2uart.v
index 7ee6554..a566b2b 100644
--- a/verilog/rtl/usb2uart.v
+++ b/verilog/rtl/usb2uart.v
@@ -10,6 +10,9 @@
     output usb_pu,  // USB 1.5kOhm Pullup EN
     output usb_tx_en  // USB tx enabled
 );
+    //115200 bauds from 48MHz clock
+    //.prescale(((48*1000000)+(115200*8)-1)/(115200*8))
+    localparam    PRESCALE = 16'h0035;
 
     wire             clk;
 
@@ -20,10 +23,6 @@
     wire [7:0]       out_data;
     wire             out_valid;
 
-    //115200 bauds from 48MHz clock
-    //.prescale(((48*1000000)+(115200*8)-1)/(115200*8))
-    reg  [15:0]      prescale = 16'h0035;
-
     assign clk = clk48;
 
     uart # (
@@ -44,7 +43,7 @@
         .m_axis_tready(in_ready),
         .rxd(uart_rx),
         
-        .prescale(prescale)
+        .prescale(PRESCALE)
     );
 
     wire             dp_pu;