| commit | 811d9dbe46da6c956e4faff7e177a72a63f08236 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Fri Jan 20 00:23:50 2023 -0800 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Fri Jan 20 00:23:50 2023 -0800 |
| tree | 7c8b09e6c4e8226634a65eeba04727088b97afef | |
| parent | c9f83622d61d88341300cf957bdea86a116b1cea [diff] |
final gds oasis
Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.
See verilog/rtl/fpga folder for FPGA tests.
mkdir -p dependencies export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src export PDK_ROOT=$(pwd)/dependencies/pdks export PDK=sky130A make setup make user_proj_example klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_proj_example.gds make user_project_wrapper klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds make verify-usb2uart-rtl make verify-usb2uart-gl #make extract-parasitics make create-spef-mapping #make caravel-sta rm -rf ~/mpw_precheck/ make precheck make run-precheck #make compress
