| commit | c9f83622d61d88341300cf957bdea86a116b1cea | [log] [tgz] |
|---|---|---|
| author | roman3017 <rbacik@hotmail.com> | Sun Jan 01 03:39:00 2023 +0000 |
| committer | roman3017 <rbacik@hotmail.com> | Sun Jan 01 03:39:00 2023 +0000 |
| tree | 7de080208e4b46d1f1f5f63cde93ec04f107fd46 | |
| parent | b8c3d42f2ea76f0579d2c11349e28c011b9967ea [diff] |
action: update build
Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.
See verilog/rtl/fpga folder for FPGA tests.
mkdir -p dependencies export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src export PDK_ROOT=$(pwd)/dependencies/pdks export PDK=sky130A make setup make user_proj_example klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_proj_example.gds make user_project_wrapper klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds make verify-usb2uart-rtl make verify-usb2uart-gl #make extract-parasitics make create-spef-mapping #make caravel-sta rm -rf ~/mpw_precheck/ make precheck make run-precheck #make compress