| commit | 9159812fac58a83c26f3b57f93e05a17544def99 | [log] [tgz] |
|---|---|---|
| author | roman3017 <rbacik@hotmail.com> | Sat Dec 31 18:19:19 2022 -0800 |
| committer | roman3017 <rbacik@hotmail.com> | Sat Dec 31 18:20:02 2022 -0800 |
| tree | 37928b9198d9541cb2d70f310572a59f7b393047 | |
| parent | 1a29b29ba1a202723e482947f7c166b0c96534dc [diff] |
move user pins from 33:37 to 16:20
Full speed USB2 to 115200 bauds UART module for TTL logic at 3V3. It requires 48MHz clock from user_clock2.
See verilog/rtl/fpga folder for FPGA tests.
mkdir -p dependencies export OPENLANE_ROOT=$(pwd)/dependencies/openlane_src export PDK_ROOT=$(pwd)/dependencies/pdks export PDK=sky130A make setup make user_proj_example klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_proj_example.gds make user_project_wrapper klayout -l dependencies/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp gds/user_project_wrapper.gds make verify-usb2uart-rtl make verify-usb2uart-gl #make extract-parasitics make create-spef-mapping #make caravel-sta rm -rf ~/mpw_precheck/ make precheck make run-precheck #make compress