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  1. 653acd4 Updating the shuttle_url value in `info.yaml` file. by Tim 'mithro' Ansell · 4 weeks ago main
  2. 2b638b3 final gds & signoff results by Jeff DiCorpo · 1 year, 1 month ago
  3. 6ec4646 final gds oasis by Jeff DiCorpo · 1 year, 1 month ago
  4. 47b0d7b final gds & signoff results by Jeff DiCorpo · 1 year, 1 month ago
  5. c4ed98a final gds & signoff results by Jeff DiCorpo · 1 year, 1 month ago

Caravel User Project

License UPRJ_CI Caravel Build

Demonstration of the Fabulous FPGA design flow using the Skywater 130 process.

This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.

Refer to README for this sample project documentation.