| commit | 2b638b3dffec6898a5555cb5bc6efdc59cc4411e | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Tue Dec 28 01:37:22 2021 +0000 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Tue Dec 28 01:37:22 2021 +0000 |
| tree | 2d824e01ce1113a2b6161d812b88939db768d585 | |
| parent | 6ec46460b96538a0fe0374d35b96dae4ddd2a4cd [diff] |
final gds & signoff results
Demonstration of the Fabulous FPGA design flow using the Skywater 130 process.
This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.
Refer to README for this sample project documentation.