foundryslot-001AXI DMA using Spinal HDL: This is a DMA controller with AMBA AXI4 interface.slot-002Wishbone CAN: An implementation of a CAN bus controller as a wishbone peripheral for the open MPW shuttle.slot-003Analog Neuron: Analog implementation of the artificial Neuron used in neural networks.slot-004caravel_dsp2: DSP Functions.slot-005FABulous_Sky: Demonstration of the Fabulous FPGA design flow using the Skywater 130 process.slot-006Opencryo_testchip: NMOS and PMOS array, ring oscillator and inductor for cryogenic characterization.slot-007YiFive (Risc V Based SOC): 32 Bit Risc SOC Design with Quad SPI , 8 bit SDRAM Controller , UART, I2C Master and USB 1.1 Host.slot-008Lexicon: This Is A Machine-Mode (M-Mode) Only, 32-Bit Cpu Small Core Which Supports Risc-V’s Integer (I), Compressed Instruction (C), Multiplication And Division (M), And Instruction-Fetch Fence, And Csr Extensions.slot-009UCSC OpenRAM Test Chip: Test chip for single and dual port memories created by OpenRAM.slot-010YONGA-LZ4 Decoder: YONGA-LZ4 Decoder Is An Implementation Of The Decoder Of The Popular Lz4 Compression Algorithm.slot-011Potentiometric_Di...: The project aims to design a 10-bit Potentiometric Digital to Analog Converter(DAC).slot-012FuseRISC: FuseRISC will demonstrate the benefits of the tight coupling of RISC-V cores and eFPGA fabric for tensorflow micro applications.slot-013Amsat TXRX IC MPW2: This step in the development and prototyping of the Amateur Radio Satellite Transceiver project contains: 150 MSPS differential current steering DAC with dynamic element matching 8 GHz differential Colpitts topology VCO Baseband to IF mixer High-speed buffer amplifier RF IO driver which can be combined with an off-chip distributed balun to drive off chip loads.slot-014Comparator VCO...: Comparator at 3v3 Supply Voltage Voltage Controlled Oscillator with 7 stage ring oscillator (120 MHz to 350 MHz).slot-015Caravel_Multi_encoder: Multi purpose integrated encoder.slot-016Kasirgalabs UART: Simple UART controller.slot-017slot-018uqab: uqab is an SoC.slot-019slot-020caravel_dsc: Caravel Harness based Digital Signal Controller for Embedded Control applications , the user project area has PTC (PWM , Timer and Input Capture) , PID controller , I2C and RTC.slot-021SOFA Plus FPGA: SOFA (Skywater Opensource FPGAs) are a series of open-source FPGA IPs using the open-source Skywater 130nm PDK and OpenFPGA framework.slot-022darkriscv in openlane: The project is a realization of darkriscv processor using openlane and skywater pdk.slot-023General_Purpose_B...: A General Purpose Bandgap Reference IP block that generates constant voltage at output, which is independent of Temperature and Supply variations.slot-024multi project harness v2: saves space on the shuttle by aggregating up to 16 designs in one submission.slot-025Fast GCD for...: Computes the Bezout coefficients associated with 1024 bit numbers with a GCD of 1.slot-026Columbus: Analog Test Chip Consisting of the following: LDO, Load Switch, Bandgap Reference, and an OpAmp.slot-027Space_Shuttle: The main goal of this project is to assess the reliability of the SkyWater 130nm manufacturing process and Open Source PDK, as well as to evaluate different reliability mitigation techniques.slot-028Subservient: ASIC adaption of SERV, the award-winning bit serial RISC-V processor.slot-029caravel_analog_fulgor: Analog test chip with master's thesis prototypes: - 1GHz Current Starved VCO - Residual amplifier with gain and variable output common mode.slot-030Bandgap_Reference_Design: A Bandgap Reference Circuit To Generate A Constant Voltage Output That Is Insensitive To Temperature And Supply Voltage Variations.slot-031RenML: A small, Convolutional Neural Network Accelerator on a wishbone slave for Raven Core in Caravel SoC.slot-032io_expander: A gpio expander for the caravel harness to realize a small microcontroller.slot-033Digital PLL: Integer Digitall PLL + LDO + Bandgap + Error Amplifier Design.slot-034multi project harness v2: saves space on the shuttle by aggregating up to 16 designs in one submission.slot-035Caravel_FPU: Caravel_FPU integrates floating point unit with Caravel Core.slot-036BrqRV_EB1: BrqRV EB1 is a machine-mode (M-mode) only, 32-bit CPU small core which supports RISC-V’s integer (I), compressed instruction (C), multiplication and division (M), and instruction-fetch fence, and CSR extensions.slot-037Hilas Analog...: Analog std cells and test structures for audio processing and analog computing.slot-038vlsi-sky130-analo...: First try at open mpw: simple analog circuits.slot-039SHA1 engine: The SHA1 engine, while not the most secure nowadays is still used by git commits and TPM PCR values.slot-040OpenFASOC: This testchip is a demonstrator of our automated analog generators within an SoC implementation. 