FuseRISC: FuseRISC will demonstrate the benefits of the tight coupling of RISC-V cores and eFPGA fabric for tensorflow micro applications.

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  1. d08e336 Updating the shuttle_url value in `info.yaml` file. by Tim 'mithro' Ansell · 1 year, 2 months ago main
  2. 3e4b342 final gds & signoff results by Jeff DiCorpo · 2 years, 2 months ago
  3. 4468196 final gds oasis by Jeff DiCorpo · 2 years, 2 months ago
  4. 0594990 final gds & signoff results by Jeff DiCorpo · 2 years, 2 months ago
  5. 82a158b final gds oasis by Jeff DiCorpo · 2 years, 2 months ago


License UPRJ_CI Caravel Build

Fuserisc2 is a Heterogeneous Multicore SoC, integrating a customised embedded FPGA fabric and two RISC-V cores (modified IBEX cores from LowRISC). The SoC uses two custom interconnects, one read the other read/write. These provide the cores with access to the SRAM and peripheral memory space. The Caravel subsystem interfaces via a wishbone to the RW interconnect, to access the FuseRISC2 address space. There is an alternative path to the SoC off chip via a custom UART to memory interface. LA and IO pins are used to provide control signals into the SoC for core and eFPGA management, these functions can also be accessed off chip. Both RISC-V cores are connected to the eFPGA fabric via a custom instruction interface (CIF). This interface uses the custom instruction window in the RISC-V specification and is encoded into the IBEX instruction decode unit. The CIF presents two operands from a core to the eFPGA fabric and enables the choice of three result paths. CIF instructions can use a flow control between the core and the fabric or use a delay. Both cores also have their interrupt hardware connected to the eFPGA, this enables dynamic core to core signalling.

The eEPGA fabric has been arranged in a T shape to best utilise the available space. Cores and SRAMS are paired, with channels through the fabric to providing space to route the interconnect.

The processor was generated using the FABulous eFPGA framework. The framework enables the user to specify the configuration of the cores, sram and eFPGA fabric with reduced engineer input compared to building RTL from scratch. We are currently porting the tensorflow micro software stack to enable the easy design and testing of AI accelerated codes on tightly coupled CPU eFPGA enabled SOC.