Table of contents
YONGA-LZ4 Decoder is an implementation of the decoder of the popular LZ4 compression algorithm.
- This test is meant to verify that we can read and write to the YONGA-LZ4 Decoder through the WISHBONE port. The firmware first writes a compressed data stream to input FIFO of the YONGA-LZ4 Decoder, then reads decoded data stream from output FIFO of the YONGA-LZ4 Decoder.
To run RTL simulation,
Hardening the User Project Macro using OpenLANE
# Run openlane to harden user_proj_example
# Run openlane to harden user_project_wrapper
Checklist for Open-MPW Two Submission
- [x] The project repo adheres to the same directory structure in this repo
- [x] The project repo contain info.yaml at the project root
- [x] Top level macro is named
- [x] Full Chip Simulation passes for RTL and GL (gate-level)
- [x] The hardened Macros are LVS and DRC clean
- [x] The hardened
user_project_wrapper adheres to the same pin order specified at pin_order
- [x] XOR check passes with zero total difference.
- [x] Openlane summary reports are retained under ./signoff/
List of Contributors
In alphabetical order:
- Abdullah Yildiz
- Altug Somay
- Burak Yakup Cakar
- Muhammed Bahadir Turkoglu
- Rifat Demircioglu