This is a DMA controller with AMBA AXI4 interface. This DMA controller is part of an ongoing effort to build an SoC with the state-of-art open source hardware development kits, such as Spinal HDL and cocotb.
Spinal HDL is a very powerful hardware description language, which is especially suitable for SoC or FPGA. Spinal HDL leverages many advanced language features from Scala, such as functional, object-oriented programming, to facilitate hardware development, which overcomes many shortages of traditional HDL, e.g. Verilog and VHDL. With Spinal HDL, the RTL code becomes much concise, error-prone, parameterized, and most important code-reuse friendly.
Spinal HDL will generate Verilog or VHDL code to be used in synthesis, since currently no synthesizer supports Spinal HDL.
cocotb is a Python-based simulation library, which supports many mainstream simulators, from
VCS, etc. Since cocotb is implemented in Python, it's much easier than SystemVerilog or C to build a reference model by leveraging abundant libraries in Python ecosystem, such as SciPy and NumPy for easy algorithm implementation, Scrapy for network communication, etc. Also, implementing test bench in cocotb is quite concise, reduces much verbosity.
This DMA controller is very flexible:
To ease debug this DMA controller, we also implemented an SDRAM controller with AMBA AXI4 interface. The SDRAM controller assumes to store data in a Micron SDRAM
MT48LC16M16A2, this Micron SDRAM has 16-bit data width. This SDRAM controller is quite flexible too:
To test the SDRAM controller, Micron provided an SDRAM reference model in Verilog, we use cocotb to test SDRAM controller w.r.t. the SDRAM reference model.
To compatible with Caravel user project, the Spinal HDL, cocotb code is separated from Caravel user project code.
The Spinal HDL and cocotb code is located in spinal-cocotb. Some important code files are:
To build and test the Spinal HDL code, there are two shell scripts:
run.sh script will generate the Verilog code,
DmaMem.v, under spinal-cocotb, which is used in Caravel user project for post-processing.
DmaMem.v will be moved to the Verilog code directory of the Caravel user project.
The Caravel user project follows the code structure of the example project exactly. Some important code files are: