| commit | 47b0d7b78c5cef79e5ac21eae01f277925d9604a | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Mon Dec 27 09:04:12 2021 +0000 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Mon Dec 27 09:04:12 2021 +0000 |
| tree | 308cc99a6bda6beae5c7d2089881616ee265d673 | |
| parent | c4ed98a9b9deaf8fd329ad3dd90b984090fcf758 [diff] |
final gds & signoff results
Demonstration of the Fabulous FPGA design flow using the Skywater 130 process.
This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.
Refer to README for this sample project documentation.