| commit | c4ed98a9b9deaf8fd329ad3dd90b984090fcf758 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Mon Dec 27 04:07:59 2021 +0000 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Mon Dec 27 04:07:59 2021 +0000 |
| tree | cc73c0ef1fa270e7b39bbd7b3e5655002d132dac | |
| parent | 61d17a2f8d9687fa4ea9d21595fae15ad22462ba [diff] |
final gds & signoff results
Demonstration of the Fabulous FPGA design flow using the Skywater 130 process.
This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.
Refer to README for this sample project documentation.
