|author||Tim 'mithro' Ansell <firstname.lastname@example.org>||Thu Dec 29 23:53:20 2022 +0000|
|committer||Tim 'mithro' Ansell <email@example.com>||Thu Dec 29 23:53:20 2022 +0000|
Updating the shuttle_url value in `info.yaml` file. Signed-off-by: Tim 'mithro' Ansell <firstname.lastname@example.org>
Demonstration of the Fabulous FPGA design flow using the Skywater 130 process.
This repo experiments an implementation of an FPGA from RTL to GDS with open Skywater-130 PDK. The design RTL was generated by FABulous framework. The fabric consists of 896 LUT4s (16x7 CLBs), 64 LUT5s (16x1 RegFiles), 8 DSPs and 8 BRAMs (8x1KB) with dual-ported memory blocks for register files and FIFOs. An embedded UART for configurations and CPU_IO interface (e.g. to RISC-V core) were also implemented in this version.
Refer to README for this sample project documentation.