CMOS High Speed...: This is a novel dynamic comparator design that improves the common mode performance.

Clone this repo:


  1. 1bf373a final gds oasis by Jeff DiCorpo · 1 year, 1 month ago main
  2. 27c4aa6 initial commit by komalkrishna5 · 1 year, 9 months ago

CMOS Rail-To-Rail Comparator

This project is the implementation of a simple rail-to-rail comparator with its bias circuitry using Skywater 130nm technology. The purpose of this project is to test the open source tools provided with the PDK and to go through all the steps of the analog design flow. Two different circuits are instantiated in the analog version of the caravel:

  • A CMOS push-pull comparator with 2 differential pairs (NMOS and PMOS).
  • A bootstrap current reference.

CMOS Comparator

The schematic of the comparator was deisgned as follows : Comparator

Bias circuit

The schematic of the bias circuit was deisgned as follows : Comparator Bias


We simulated the comparator with a voltage ramp at the negative input and a sinusoidal signal at the positive input. The output is a digital signal that triggers at the intersection of the 2 analog input signals. Simulation