foundryslot-001Free and open...: Hardware accelerator that implements standard encryption algorithm AES ECB.slot-002Microwatt MPW6: Microwatt is a 64 bit OpenPOWER core written in VHDL.slot-003Hack SoC - MPW-6: Hardware implementation of the Hack Computer from the Nand to Tetris courses.slot-004Riscduino-DCore(D3): Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arduino platform and this soc targeted for efabless Shuttle program.slot-005Riscduino-QCore(Q2): Riscduino is a Quad 32 bit RISC V based SOC design pin compatible to arduino platform and this soc targeted for efabless Shuttle program.slot-006Riscduino-SCore(S4): Arduino pin compatible Single RISCV 32 Bit core Project.slot-007SonaronChip8: process acoustics signals from 8 MEMS microphones with an extended frequency range up to 85 kHz (low ultrasonic band).slot-008FT8 Receiver Test: A sample tapeout to test needed circuitry for a fully-functional FT8 transceiver.slot-009Azadi_DFT: This project is the extended version of Azadi-SoC, which includes all of the peripherals which were in Azadi-II and few more this time, which were not stable at the time of Azadi-II.slot-010SRAMTestVehicleSequel: Iteration on SRAM test vehicle that was not selected for MPW5.slot-011ISA 16 bit Microprocessor: This is simple microprocessor.slot-012Asicle rollover: Have you played Wordle on raw silicon yet? (This is a resubmission from MPW5.).slot-01310b ADC and...: This submission features: 10b SAR-ADC, Bandgap reference, Testbuffer, Clock generator, LDO, Bias Network.slot-014YONGA-Modbus Controller: A Modbus controller which has a read(03h) and a write(10h) function.slot-015ChristmasTreeCont...: Christmas tree controller (MPW5 ReRun).slot-016OpenRAM Test Design: This project was designed to be able to test the SRAM macros generated using OpenRAM flow.slot-0174 x PWM: PWM (Pulse Width Modulation) modules (resubmission from MPW-5).slot-018HyperRAM Interface: Resubmission of Steve Goldsmith's project.slot-019Adaptive...: We make implementation of a flexible 32-point Discrete Cosine Transform (DCT).slot-020CMOS cascode...: This is a high speed dynamic comparator.slot-021CMOS High Speed...: This is a novel dynamic comparator design that improves the common mode performance.slot-022ORDER_PRGA_MPW6: A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array); An 8x8 array of CLBsslot-023Temporal Runtime...: This is a specialized on-chip microcontroller/SoC component for performing runtime monitoring of temporal logic formulas.slot-024MARMOT RISC-V SOC: Targeting 5-year continuous operation, a solar panel, a power supply board, a logic board, and lithium batteries are to be integrated in a waterproof housing to form an IoT.slot-025RNG MULTI SCROLL CHAOS: In this study, a digital RNG based on chaotic oscillators was implemented using the SKY130 process node.slot-026Mixed_signal_circ...: Basic ReRAM, Floating Gate, and other analog structures.slot-027Mixed_signal_circuits_v2: Mixed signal circuits for analog synapses.slot-028direct...: This project contains blocks of a receiver.slot-029Floating_Point_Un...: This is the Floating point unit which supports the IEEE-754 Half Precision format.slot-030Floating_Point_Un...: This is the first ever Bfloat16 precision floating point unit designed by undergraduate students of DHA Suffa University Pakistan.slot-031Floating_Point_Un...: This is the first ever Single Precision Floating Point Unit designed by Undergraduate Students of DHA Suffa Univeristy.slot-032Experiar SoC: Experiar SoC is a dual RV32I core processor with peripherals including PWM, SPI, UART, and VGA.slot-033my_caravel_analog_project: This is my first project. 6-bit saradc.slot-034Efabless_MPW6_riscduino: This is a clone project from dineshannayya/riscduino.slot-035Motius Pong: The first game: PONG.slot-036SoC_Now: This SoC is generated by the SoC Now Generator which is the final year project of undergraduate students.slot-037ORDER_PRGA_MPW6_v2: A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array); An 8x8 array of CLBsslot-038Optimised Strong...: This is the design of an optimised Strong ARM Latch using modified particle swarm optimisation.slot-039riscduino_qcore_folk: folk of riscduino_qcore for test.slot-040Tensor...: Using NNgen to generate circuits.