Clone this repo:

Branches

  1. f2e7284 final gds oasis by Jeff DiCorpo · 10 weeks ago main
  2. 67489f9 Added spi ip by Aloke Das · 3 months ago
  3. 28408bf Modified cpu RTL to stop clock after HALT instruction by Aloke Das · 6 months ago
  4. 15d8c5e Fixed bug is address read by Aloke Das · 6 months ago
  5. 89dd51b Changes related to additon of 8KB SRAM by Aloke Das · 6 months ago

ISA 16-bit microprocessor

This is the next version of the SOC. 8KB of memory has been added. The memory can be loadded via logic analyzer bus from management core. Then the program and data can be used from memory.

The clock can be chosen from wishbone clock or user_clock2 or external. The reset can be chosen from wishbone reset or external pin. A soc configuration block has been aceated to control memory and cpu.