Clone this repo:


  1. b18a19a final gds oasis by Jeff DiCorpo · 10 weeks ago main
  2. b303a32 [GDS/RTL] Updated top/user_project_wrapper GDS by Ang Li · 8 months ago
  3. 5e0d69c [CFG] Update prga pin_order.cfg by Ang Li · 8 months ago
  4. 0077f3e [RTL] Cannot add logic in user_project_wrapper... by Ang Li · 8 months ago
  5. e9a9899 [TB] Fixed IO connections by Ang Li · 8 months ago


This repository is a branch of the caravel_user_project repository, modified for the tapeout of a 512-LUT4 FPGA generated using PRGA.

A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array)

  • An 8x8 array of CLBs, each containing 8 LUT4s and 8 DFFs and a local programmable crossbar for intra-CLB routing
  • 24-track routing channel with L1 tracks
  • Capable of implementing 16 out of 30 ISCAS'89 circuits

License UPRJ_CI Caravel Build


We used a three level hierarchical design:

  • 1x Caravel user project wrapper
    • 1x PRGA top
      • 64x CLB tile