Google Git
Sign in
foss-eda-tools / third_party / shuttle / sky130 / mpw-006 / slot-037 / 0077f3e8a2f07b8a88e582d5c44f89006e95dd99
commit0077f3e8a2f07b8a88e582d5c44f89006e95dd99[log] [tgz]
authorAng Li <angl@princeton.edu>Sat May 21 15:49:56 2022 -0400
committerAng Li <angl@princeton.edu>Sat May 21 15:49:56 2022 -0400
treedce8af0cac04bf0acd9da2b1ea156db136e0ed28
parente9a9899b37b6f857968780395b4e69f1fc4d27e3 [diff]
[RTL] Cannot add logic in user_project_wrapper...

... Push output-enable inversion into `top`
2 files changed
tree: dce8af0cac04bf0acd9da2b1ea156db136e0ed28
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. .gitignore
  13. LICENSE
  14. Makefile
  15. README.md
README.md

ORDER PRGA Tapeout

This repository is a branch of the caravel_user_project repository, modified for the tapeout of a 512-LUT4 FPGA generated using PRGA.

A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array)

  • An 8x8 array of CLBs, each containing 8 LUT4s and 8 DFFs and a local programmable crossbar for intra-CLB routing
  • 24-track routing channel with L1 tracks
  • Capable of implementing 16 out of 30 ISCAS'89 circuits

License UPRJ_CI Caravel Build

Design

We used a three level hierarchical design:

  • 1x Caravel user project wrapper
    • 1x PRGA top
      • 64x CLB tile