)]}'
{
  "commit": "0077f3e8a2f07b8a88e582d5c44f89006e95dd99",
  "tree": "dce8af0cac04bf0acd9da2b1ea156db136e0ed28",
  "parents": [
    "e9a9899b37b6f857968780395b4e69f1fc4d27e3"
  ],
  "author": {
    "name": "Ang Li",
    "email": "angl@princeton.edu",
    "time": "Sat May 21 15:49:56 2022 -0400"
  },
  "committer": {
    "name": "Ang Li",
    "email": "angl@princeton.edu",
    "time": "Sat May 21 15:49:56 2022 -0400"
  },
  "message": "[RTL] Cannot add logic in user_project_wrapper...\n\n... Push output-enable inversion into `top`\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "70b1ad876d7d5acceae29aea5f25c5bba5ddb64a",
      "old_mode": 33188,
      "old_path": "verilog/rtl/top.pickled.v",
      "new_id": "4f141eb563102b0513135b3660299377953bcc9d",
      "new_mode": 33188,
      "new_path": "verilog/rtl/top.pickled.v"
    },
    {
      "type": "modify",
      "old_id": "2e985928670f1769c444fdedc2b273de993b55b6",
      "old_mode": 33188,
      "old_path": "verilog/rtl/user_project_wrapper.v",
      "new_id": "c495ada081606dead7dad24b65848567f2327256",
      "new_mode": 33188,
      "new_path": "verilog/rtl/user_project_wrapper.v"
    }
  ]
}