Systolic Array...: Systolic Array is a classical architecture that is recently revitalized among Neural Network accelerator designs.

Clone this repo:

Branches

  1. d7a9686 final gds oasis by Jeff DiCorpo · 1 year, 3 months ago main
  2. f9d3848 update by ianboyanzhang · 1 year, 4 months ago
  3. 4d320ce Add {user}_defines.v by ianboyanzhang · 1 year, 4 months ago
  4. b4409ff Update README.md by Ian Zhang · 1 year, 7 months ago
  5. 2e8c111 Update README.md by Ian Zhang · 1 year, 7 months ago

Caravel User Project

MPW 7 Systolic Array submission

Systolic Array is a classical architecture that is recently revitalized among Neural Network accelerator designs.

It is the heart of Google's TPUs and major workhorses of DSP engines.

In this project, we manually build a 3x3 matrix multiplier with Multiply-Accumulate Units that support two popular data formats used in modern machine learning or neural networks applications.

FP16 and int8 modes are runtime configurable through the Caravel SoC core. The design is focusing on clean coding for ease of understanding and proper modulation for future extension.

Huge shoutout and appreciation to Steve @https://aurifexlabs.com/ for his invaluable assistance with Caravel.