YONGA-CAN Controller: YONGA-CAN Controller is a partial implementation of CAN 2.0B standard.

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Caravel User Project

License UPRJ_CI Caravel Build

YONGA-CAN Controller

YONGA-CAN Controller is a partial implementation of CAN 2.0B standard. Currently supported functionalities are:

  • Transmit DATA FRAME in standard format

Register Map

OffsetNameDescriptionType
0x0BAUD_RATE_CFGBaud Rate Configuration RegisterREG
0x4MSG_IDMessage ID RegisterREG
0x8MSG_CFGMessage Type and Length RegisterREG
0xCDATA_REG1Data Register 1REG
0x10DATA_REG2Data Register 2REG
0x14SYS_CFGIP Config RegisterREG
0x18SYS_CTRL_STSIP Control and Status RegisterREG

Registers

OffsetNameDescriptionTypeAccessAttributesReset
0x0BAUD_RATE_CFGBaud Rate Configuration RegisterREGR/W0x0
[8:0] TSEG2Time Quanta Count for Phase Buffer Segment 20x0
[17:9] TSEG1Time Quanta Count for Propagation Time Segment and Phase Buffer Segment 10x0
[26:18] BRPBaud Rate Prescaler0x0
[31:27] SJWSyncronization Jump Width0x0
0x4MSG_IDMessage ID RegisterREGR/W0x0
[17:0] EIDMessage EID0x0
[18] IDEMessage ID Extension Flag0x0
[29:19] SIDMessage SID0x0
0x8MSG_CFGMessage Type and Length RegisterREGR/W0x0
[3:0] DLCData Length Code0x0
[4] RTRRemote Transmit Request Flag0x0
0xCDATA_REG1Data Register 1REGR/W0x0
[7:0] DATA_BYTE_0Data Byte 00x0
[15:8] DATA_BYTE_1Data Byte 10x0
[23:16] DATA_BYTE_2Data Byte 20x0
[31:24] DATA_BYTE_3Data Byte 30x0
0x10DATA_REG2Data Register 2REGR/W0x0
[7:0] DATA_BYTE_4Data Byte 40x0
[15:8] DATA_BYTE_5Data Byte 50x0
[23:16] DATA_BYTE_6Data Byte 60x0
[31:24] DATA_BYTE_7Data Byte 70x0
0x14SYS_CFGIP Config RegisterREGR/W0x0
[0] MODEIP Mode Select0x0
BUS_MODE = 0, LOOPBACK_MODE = 1
[1] ENABLEIP Enable Flag0x0
0x18SYS_CTRL_STSIP Control and Status RegisterREGR/W0x0
[0] SENDSend Messageself-clearing0x0
[3:1] STATUS_CODEOperation Status Code0x0
TX_SUCCESSFUL = 1, ARBITRATION_LOST = 2, TX_FAILED = 4

Generated on 2022-09-06 at 12:53 (UTC) by airhdl version 2022.08.2-618538036

Running Simulation

TX Test

  • This test is meant to verify that we can send a DATA FRAME in standard format.

To run RTL simulation,

cd $UPRJ_ROOT
make verify-can_test_1-rtl

Hardening the User Project Macro using OpenLANE

cd $UPRJ_ROOT

# Run openlane to harden user_proj_example
make user_proj_example

# Run openlane to harden user_project_wrapper
make user_project_wrapper

List of Contributors

In alphabetical order:

  • Hanim Ay
  • Okan Yagiz