Clone this repo:

Branches

  1. f490c96 final gds oasis by Jeff DiCorpo · 7 days ago main
  2. 8d8fd9c Update README.md by rakshit-23 · 7 weeks ago
  3. 1f0e1da Update user_defines.v by rakshit-23 · 7 weeks ago
  4. 5e64659 Update user_proj_example.v by rakshit-23 · 7 weeks ago
  5. 3d500c2 Initial commit by rakshit-23 · 7 weeks ago

Caravel User Project

License UPRJ_CI Caravel Build

:exclamation: Important Note

The universal shift register features parallel load, left-shift and right-shift serial input, and synchronous active high reset. The registers have 4 modes of operation out of which 1 is operational according to the select lines. The 4 modes of operation are:

Shift left Shift right Parallel load Temporary storage Parallel synchronous loading is accomplished by applying the four bits of data and taking S0 low and S1 high. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock input. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When both S0 and S1 are low, data shifts left synchronously and new data is entered at the shift-left serial inputs. When both S0 and S1 are high, the data inside the bidirectional shift register does not change. Synchronous active high clear signal is used to reset the bidirectional shift register.