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  1. fea41c0 final gds oasis by Jeff DiCorpo · 7 days ago main
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  3. cff1cf5 Initial commit by mohithharsha · 4 weeks ago

Open Source Digital ASIC Design requires three open-source components:

RTL Designs = github.com, librecores.org, opencores.org
EDA Tools = OpenROAD, OpenLANE,QFlow
PDK = Google + Skywater 130nm Production PDK

PDK (Process Design Kit) = A set of data files and documents which serves as the interface between the designer and the fab. This includes cell libraries, IO libraries, design rules (DRC, LVS, etc.) Simplified RTL to GDSII Flow:

Sythesis = The RTL is converted into a gate level netlist made up of components of standard cell libary.
Floor Planning/ Power Planning = Plan silicon area and create robust power distribution network. The power network usually uses the upper metal layer which are thicker than lower layer and thus lower resistance. This lowers the IR drop problem
Placement = There are two steps, first is global placement which is the general optimal positons for cells and might not be legal. Next is detailed placement which is the actual legal placements of the cells.
Clock tree synthesis = clock distribution is usually a tree (H-tree, X-tree ... )
Routing = Use horizontal and vertical wires to connect cells together. The router uses PDK information (thickness, pitch, width,vias) for each metal layer to do the routing. The Sky130 defines 6 routing layers. It doe global routing and detailed routing.
Verification before sign-off = Involves physical verification like DRC and LVS and timing verification. Design Rule Checking or DRC ensures final layout honors all design rules and Layout versus Schematic or LVS ensures final layout matches the gate level netlist from synthesis phase. Timing verification ensures timing constraints are met.

The final layout is in GDSII file format.

OpenLane = An open-source ASIC development flow reference. It consists of multiple open-source tools needed for the whole RTL to GDSII flow. This is tuned epecially for Sky130 PDK. It also works for OSU 130nm. It is recommended to read the OpenLANE documentation before moving forward.

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