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Branches

  1. f4105bc final gds oasis by Jeff DiCorpo · 7 days ago main
  2. 06ceae0 Add results by mole99 · 5 weeks ago
  3. 4ef901a Remove example by mole99 · 5 weeks ago
  4. 250b195 Update wrapper by mole99 · 5 weeks ago
  5. 6a899e2 Add GL verilog by mole99 · 5 weeks ago

LeoSoC

License UPRJ_CI Caravel Build

This is a simple SoC with the following:

  • 1 LeoRV32 Core (RV32I)
  • 8 kB Work RAM
  • 8 kB Video RAM (can also be used as Work RAM)
  • SVGA Core (800 x 600, 40 MHz)
    • Resolution decreased to 100 x 75 pixel
    • 1 Byte per Pixel with direct color format (BBGGGRRR)
  • UART
    • 9600 baud fixed at 40 MHz
  • Blink
    • Simple output to blink an LED

Address Layout

PeripheralAddress
WRAM_BASE0x000000
VRAM_BASE0x010000
UART_BASE0x0A0000
BLINK_BASE0x0F0000