commit	4ef901a12f6097d75f2b87627fad310c70ec880f	[log] [tgz]
author	mole99 <leomoser99@gmail.com>	Fri Dec 23 10:29:16 2022 +0100
committer	mole99 <leomoser99@gmail.com>	Fri Dec 23 10:29:16 2022 +0100
tree	d1ce1616b0063a94fce9650610ea29d95ea3d33a
parent	250b195aaf6aef77939c933c216270e20cd4672e [diff]

Remove example

verilog/dv/init_vram/init_vram.vcd.hier[Deleted - diff]
verilog/dv/init_vram/init_vram.vvp[Deleted - diff]
verilog/rtl/user_proj_example.v[Deleted - diff]

3 files changed

tree: d1ce1616b0063a94fce9650610ea29d95ea3d33a

README.md

LeoSoC

This is a simple SoC with the following:

1 LeoRV32 Core (RV32I)
8 kB Work RAM
8 kB Video RAM (can also be used as Work RAM)
SVGA Core (800 x 600, 40 MHz)
- Resolution decreased to 100 x 75 pixel
- 1 Byte per Pixel with direct color format (BBGGGRRR)
UART
- 9600 baud fixed at 40 MHz
Blink
- Simple output to blink an LED

Address Layout

Peripheral	Address
WRAM_BASE	0x000000
VRAM_BASE	0x010000
UART_BASE	0x0A0000
BLINK_BASE	0x0F0000