commit	6a899e26429919571b563118edd03c4b08e53188	[log] [tgz]
author	mole99 <leomoser99@gmail.com>	Fri Dec 23 10:26:58 2022 +0100
committer	mole99 <leomoser99@gmail.com>	Fri Dec 23 10:26:58 2022 +0100
tree	168a46cc476d32657c29bd741f38fa76dc7b52c1
parent	40756b1fd26256373b9b8e343633e7c56320881b [diff]

Add GL verilog

verilog/gl/leorv32.nl.v[Added - diff]
verilog/gl/leorv32.v[Added - diff]
verilog/gl/soc.nl.v[Added - diff]
verilog/gl/soc.v[Added - diff]
verilog/gl/user_project_wrapper.nl.v[Added - diff]
verilog/gl/user_project_wrapper.v[diff]

6 files changed

tree: 168a46cc476d32657c29bd741f38fa76dc7b52c1

README.md

LeoSoC

This is a simple SoC with the following:

1 LeoRV32 Core (RV32I)
8 kB Work RAM
8 kB Video RAM (can also be used as Work RAM)
SVGA Core (800 x 600, 40 MHz)
- Resolution decreased to 100 x 75 pixel
- 1 Byte per Pixel with direct color format (BBGGGRRR)
UART
- 9600 baud fixed at 40 MHz
Blink
- Simple output to blink an LED

Address Layout

Peripheral	Address
WRAM_BASE	0x000000
VRAM_BASE	0x010000
UART_BASE	0x0A0000
BLINK_BASE	0x0F0000