commit	40756b1fd26256373b9b8e343633e7c56320881b	[log] [tgz]
author	mole99 <leomoser99@gmail.com>	Fri Dec 23 10:26:37 2022 +0100
committer	mole99 <leomoser99@gmail.com>	Fri Dec 23 10:26:37 2022 +0100
tree	232c1dedcd58bac83e868c56d58fd1a812c34d8c
parent	47ef9e56d93e5afd0af2804b0ccd6c6f0d78a13d [diff]

Add init_vram simulation

verilog/dv/init_vram/Makefile[Added - diff]
verilog/dv/init_vram/init_vram.c[Added - diff]
verilog/dv/init_vram/init_vram.vcd.hier[Added - diff]
verilog/dv/init_vram/init_vram.vvp[Added - diff]
verilog/dv/init_vram/init_vram_tb.v[Added - diff]

5 files changed

tree: 232c1dedcd58bac83e868c56d58fd1a812c34d8c

README.md

LeoSoC

This is a simple SoC with the following:

1 LeoRV32 Core (RV32I)
8 kB Work RAM
8 kB Video RAM (can also be used as Work RAM)
SVGA Core (800 x 600, 40 MHz)
- Resolution decreased to 100 x 75 pixel
- 1 Byte per Pixel with direct color format (BBGGGRRR)
UART
- 9600 baud fixed at 40 MHz
Blink
- Simple output to blink an LED

Address Layout

Peripheral	Address
WRAM_BASE	0x000000
VRAM_BASE	0x010000
UART_BASE	0x0A0000
BLINK_BASE	0x0F0000