Open Source Digital ASIC Design requires three open-source components:

• RTL Designs = github.com, librecores.org, opencores.org
• EDA Tools = OpenROAD, OpenLANE,QFlow
• PDK = Google + Skywater 130nm Production PDK

PDK (Process Design Kit) = A set of data files and documents which serves as the interface between the designer and the fab. This includes cell libraries, IO libraries, design rules (DRC, LVS, etc.)

Simplified RTL to GDSII Flow:

• Sythesis = The RTL is converted into a gate level netlist made up of components of standard cell libary.
• Floor Planning/ Power Planning = Plan silicon area and create robust power distribution network. The power network usually uses the upper metal layer which are thicker than lower layer and thus lower resistance. This lowers the IR drop problem
• Placement = There are two steps, first is global placement which is the general optimal positons for cells and might not be legal. Next is detailed placement which is the actual legal placements of the cells.
• Clock tree synthesis = clock distribution is usually a tree (H-tree, X-tree ... )
• Routing = Use horizontal and vertical wires to connect cells together. The router uses PDK information (thickness, pitch, width,vias) for each metal layer to do the routing. The Sky130 defines 6 routing layers. It doe global routing and detailed routing.
• Verification before sign-off = Involves physical verification like DRC and LVS and timing verification. Design Rule Checking or DRC ensures final layout honors all design rules and Layout versus Schematic or LVS ensures final layout matches the gate level netlist from synthesis phase. Timing verification ensures timing constraints are met.

The final layout is in GDSII file format.

OpenLane = An open-source ASIC development flow reference. It consists of multiple open-source tools needed for the whole RTL to GDSII flow. This is tuned epecially for Sky130 PDK. It also works for OSU 130nm. It is recommended to read the OpenLANE documentation before moving forward.

• The input for the whole flow are the rtl files, sdc file, and PDK files. The output is GDSII/LEF file.

• Yosys is used to convert the HDL to gate level netlist using generic components. The ABC script is then used to map the generic components to the standard cell library of the PDK. These ABC scripts is used to make various synthesis strategies (using the Synthesis Exploration) which can optimize the design either with least area or best timing.

• The Logic Equivalency Cheking (LEC) is used to compare the resulting netlist after optimization of place and route to the gate level netlist from synthesis phase

• Antenna Rules Violation = long wire segments will act as antennna and will accumulate charges, this might damage the connected transistor gates. Solution is to either use bridging or antenna diode insertion to leak away the charges

OpenLane Directory Hierarchy:

├── OpenLane             -> directory where the tool can be invoked (run docker first)
│   ├── designs          -> All designs must be extracted from this folder
│   │   │   ├── ksa16 -> Design used as case study for this workshop
│   |   |   ├── ...
|   |   ├── ...
├── pdks                 -> contains pdk related files 
│   ├── skywater-pdk     -> all Skywater 130nm PDKs
│   ├── open-pdks        -> contains scripts that makes the commerical PDK (which is normally just compatible to commercial tools) to also be compatible with the open-source EDA tool
│   ├── sky130A          -> pdk variant made especially compatible for open-source tools
│   │   │  ├── libs.ref  -> files specific to node process (timing lib, cell lef, tech lef) for example is `sky130_fd_sc_hd` (Sky130nm Foundry Standard Cell High Density)  
│   │   │  ├── libs.tech -> files specific for the tool (klayout,netgen,magic...) 

Inside a specific design folder contains a config.tcl which overrides the default settings on OpenLANE. These configurations are specific to a design (e.g. clock period, clock port, verilog files...). The priority order for the OpenLANE settings:

1. sky130_xxxxx_config.tcl in OpenLane/designs/[design]/
2. config.tcl in OpenLane/designs/[design]/
3. Default values in OpenLane/configuration/

The task is to find the flip-flop ratio ratio for the design ksa16. For the OpenLane installation, the steps are very straight forward and can be found on the OpenLane repo.

Set configuration variables. Before running floorplan stage, the configuration variables or switches must be configured first. The configuration variables are on openlane/configuration:

.
├── README.md      
├── checkers.tcl
├── cts.tcl
├── floorplan.tcl  
├── general.tcl
├── lvs.tcl
├── placement.tcl
├── routing.tcl
└── synthesis.tcl 

The README.md describes all configuration variables for every stage and the tcl files contain the default OpenLANE settings. All configurations accepted by the current run is on openlane/designs/ksa16/runs/config.tcl. This may come either from (with priority order):

• PDK specific configuration inside the design folder
• config.tcl inside the design folder
• System default settings inside openlane/configurations

1. Run OpenLANE:

• $ make mount = Open the docker platform inside the openlane/
• % flow.tcl -interactive = run script for automating the whole RTL to GDSII flow but in step by step -interactive mode -

% package require openlane 0.9 == retrives all dependencies for running v0.9 of OpenLANE

2. Design Setup Stage:

• % prep -design ksa16 = Setup the filesystem where the OpenLANE tools can dump the outputs. This also creates a run/ folder inside the specific design directory which contains the command log files, results, and the reports dump by each tools. These folders will be empty for now except for lef files generated by this design setup stage. This merged the cell LEF files .lef and technology LEF files .tlef generating merged.nom.lef inside run/tmp/

3. Run synthesis:

• % run_synthesis = Run yosys RTL synthesis, ABC scripts (for technology mapping), and OpenSTA.

21. Printing statistics.