PRGA-test: An initial attempt to create a Test chip.

Clone this repo:


  1. 9949afd final gds oasis by Jeff DiCorpo · 1 year, 2 months ago main
  2. bb1a4f6 Re-run timing scripts completed by Sam Lim · 1 year, 3 months ago
  3. 9d31bc4 Add missing file verilog/gl/top.v.gz by Sam Lim · 1 year, 6 months ago
  4. 8c951bd 2nd commit by Sam Lim · 1 year, 6 months ago
  5. 235e1aa Test PRGA by Sam Lim · 1 year, 6 months ago


This repository is a branch of the caravel_user_project repository, modified for the tapeout of a 512-LUT4 FPGA generated using PRGA.

The project is a test project, forked from the MPW5 PRGA project.

A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array)

  • An 8x8 array of CLBs, each containing 8 LUT4s and 8 DFFs and a local programmable crossbar for intra-CLB routing
  • 24-track routing channel with L1 tracks
  • Capable of implementing 16 out of 30 ISCAS'89 circuits

License UPRJ_CI Caravel Build


We used a three level hierarchical design:

  • 1x Caravel user project wrapper
    • 1x PRGA top
      • 64x CLB tile