Re-run timing scripts completed
3 files changed
tree: 1e50fe39cf0553713f2ffc9979616ae99f4fbc6c
  1. .github/
  2. def/
  3. deps/
  4. docs/
  5. gds/
  6. lef/
  7. mag/
  8. maglef/
  9. openlane/
  10. signoff/
  11. spi/
  12. verilog/
  13. .gitignore
  15. Makefile


This repository is a branch of the caravel_user_project repository, modified for the tapeout of a 512-LUT4 FPGA generated using PRGA.

The project is a test project, forked from the MPW5 PRGA project.

A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array)

  • An 8x8 array of CLBs, each containing 8 LUT4s and 8 DFFs and a local programmable crossbar for intra-CLB routing
  • 24-track routing channel with L1 tracks
  • Capable of implementing 16 out of 30 ISCAS'89 circuits

License UPRJ_CI Caravel Build


We used a three level hierarchical design:

  • 1x Caravel user project wrapper
    • 1x PRGA top
      • 64x CLB tile