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foss-eda-tools / third_party / shuttle / sky130 / mpw-007 / slot-040 / 9d31bc41efe1511f3d4835c18c05ffa8847f25eb
commit9d31bc41efe1511f3d4835c18c05ffa8847f25eb[log] [tgz]
authorSam Lim <cmfbook@gmail.com>Mon Sep 12 01:46:43 2022 -0700
committerSam Lim <cmfbook@gmail.com>Mon Sep 12 01:46:43 2022 -0700
tree7dffee7b5fa9fe423e751e2d6517725521fb7274
parent8c951bd8088d6e41eda870c0e61821ac0974ad8c [diff]
Add missing file verilog/gl/top.v.gz
1 file changed
tree: 7dffee7b5fa9fe423e751e2d6517725521fb7274
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. mag/
  7. maglef/
  8. openlane/
  9. signoff/
  10. spi/
  11. verilog/
  12. .gitignore
  13. LICENSE
  14. Makefile
  15. README.md
README.md

ORDER PRGA Tapeout

This repository is a branch of the caravel_user_project repository, modified for the tapeout of a 512-LUT4 FPGA generated using PRGA.

The project is a test project, forked from the MPW5 PRGA project.

A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array)

  • An 8x8 array of CLBs, each containing 8 LUT4s and 8 DFFs and a local programmable crossbar for intra-CLB routing
  • 24-track routing channel with L1 tracks
  • Capable of implementing 16 out of 30 ISCAS'89 circuits

License UPRJ_CI Caravel Build

Design

We used a three level hierarchical design:

  • 1x Caravel user project wrapper
    • 1x PRGA top
      • 64x CLB tile