)]}'
{
  "commit": "9d31bc41efe1511f3d4835c18c05ffa8847f25eb",
  "tree": "7dffee7b5fa9fe423e751e2d6517725521fb7274",
  "parents": [
    "8c951bd8088d6e41eda870c0e61821ac0974ad8c"
  ],
  "author": {
    "name": "Sam Lim",
    "email": "cmfbook@gmail.com",
    "time": "Mon Sep 12 01:46:43 2022 -0700"
  },
  "committer": {
    "name": "Sam Lim",
    "email": "cmfbook@gmail.com",
    "time": "Mon Sep 12 01:46:43 2022 -0700"
  },
  "message": "Add missing file verilog/gl/top.v.gz\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "987081bf4d30b1208a5d7e7c51a5c17bf2645bbf",
      "new_mode": 33188,
      "new_path": "verilog/gl/top.v.gz"
    }
  ]
}