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  1. a1fbc0d final gds oasis by Jeff DiCorpo · 6 weeks ago main
  2. 6774e66 Re-harden by Mathis Salmen · 8 weeks ago
  3. d9a00d8 Reduced routing by Mathis Salmen · 8 weeks ago
  4. 52d5fee Updated readme by Mathis Salmen · 8 weeks ago
  5. 258aa6f Inital commit. by Mathis Salmen · 8 weeks ago

SoomRV

License UPRJ_CI Caravel Build

Description

SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute up to 4 Instructions per cycle completely out of order, and also supports speculative execution and precise exceptions.

Features

  • RV32IMCZfinxZbaZbbZicbom Instruction Set (other instructions can be emulated via traps)
  • 4-wide, Ports: 2 Integer/FP, 1 Load, 1 Store
  • Fully Out-of-Order Load/Store
  • TAGE-Predictor with 64-entry 8-way associative BTB.
  • Tag-based OoO execution, 64 registers
  • 64 entry Reorder Buffer
  • 4KiB ICache + 4KiB DCache
  • 32-bit bus (on GPIOs) for memory expansion

Repo

The Verilog source files can be found in verilog/rtl. These are converted from SystemVerilog via zachjs' sv2v, the original SystemVerilog source code is available here.