| commit | d9a00d8f8ce90d3b63cee7abf2441dcd762f4975 | [log] [tgz] |
|---|---|---|
| author | Mathis Salmen <mathis.salmen@matsal.de> | Sun Dec 04 22:37:05 2022 +0100 |
| committer | Mathis Salmen <mathis.salmen@matsal.de> | Sun Dec 04 22:37:05 2022 +0100 |
| tree | f2a658d6d1ce0830e0a011a3b62c5beafaee4d1a | |
| parent | 52d5fee7819129279d3f9c6bba1446c6919b672b [diff] |
Reduced routing
SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute up to 4 Instructions per cycle completely out of order, and also supports speculative execution and precise exceptions.
The Verilog source files can be found in verilog/rtl. These are converted from SystemVerilog via zachjs' sv2v, the original SystemVerilog source code is available here.