Google Git
Sign in
foss-eda-tools / third_party / shuttle / sky130 / mpw-007 / slot-018 / 52d5fee7819129279d3f9c6bba1446c6919b672b
commit52d5fee7819129279d3f9c6bba1446c6919b672b[log] [tgz]
authorMathis Salmen <mathis.salmen@matsal.de>Sun Dec 04 01:50:16 2022 +0100
committerMathis Salmen <mathis.salmen@matsal.de>Sun Dec 04 01:50:16 2022 +0100
tree570e1e4ebbee60847d4ccf5ca09a5cc81a5ee176
parent258aa6f7a55cbf30da7b3560ab44bce43f80cb91 [diff]
Updated readme
1 file changed
tree: 570e1e4ebbee60847d4ccf5ca09a5cc81a5ee176
  1. .github/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. lib/
  7. mag/
  8. maglef/
  9. openlane/
  10. sdc/
  11. sdf/
  12. signoff/
  13. spef/
  14. spi/
  15. verilog/
  16. .gitignore
  17. LICENSE
  18. Makefile
  19. README.md
README.md

SoomRV

License UPRJ_CI Caravel Build

Description

SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute up to 4 Instructions per cycle completely out of order, and also supports speculative execution and precise exceptions.

Features

  • RV32IMCZfinxZbaZbbZicbom Instruction Set (other instructions can be emulated via traps)
  • 4-wide, Ports: 2 Integer/FP, 1 Load, 1 Store
  • Fully Out-of-Order Load/Store
  • TAGE-Predictor with 64-entry 8-way associative BTB.
  • Tag-based OoO execution, 64 registers
  • 64 entry Reorder Buffer
  • 4KiB ICache + 4KiB DCache
  • 32-bit bus (on GPIOs) for memory expansion

Repo

The Verilog source files can be found in verilog/rtl. These are converted from SystemVerilog via zachjs' sv2v, the original SystemVerilog source code is available here.