|author||Jeff DiCorpo <firstname.lastname@example.org>||Sat Dec 17 12:54:14 2022 -0800|
|committer||Jeff DiCorpo <email@example.com>||Sat Dec 17 12:54:14 2022 -0800|
final gds oasis
SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute up to 4 Instructions per cycle completely out of order, and also supports speculative execution and precise exceptions.
The Verilog source files can be found in
verilog/rtl. These are converted from SystemVerilog via zachjs' sv2v, the original SystemVerilog source code is available here.