| commit | a1fbc0d7d6b3ab793872600a956e465880d96042 | [log] [tgz] |
|---|---|---|
| author | Jeff DiCorpo <jeffdi@efabless.com> | Sat Dec 17 12:54:14 2022 -0800 |
| committer | Jeff DiCorpo <jeffdi@efabless.com> | Sat Dec 17 12:54:14 2022 -0800 |
| tree | 9fd1942334717ccf9d76a855fa7cfa70d78a1343 | |
| parent | 6774e665e8059df37f5c31f35ad7b445973a21dc [diff] |
final gds oasis
SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute up to 4 Instructions per cycle completely out of order, and also supports speculative execution and precise exceptions.
The Verilog source files can be found in verilog/rtl. These are converted from SystemVerilog via zachjs' sv2v, the original SystemVerilog source code is available here.
