commit	258aa6f7a55cbf30da7b3560ab44bce43f80cb91	[log] [tgz]
author	Mathis Salmen <mathis.salmen@matsal.de>	Sun Dec 04 01:34:32 2022 +0100
committer	Mathis Salmen <mathis.salmen@matsal.de>	Sun Dec 04 01:34:32 2022 +0100
tree	92767a0278d68a6a71e49a0379c8cab9d9a2f627

Inital commit.

.github/workflows/user_project_ci.yml[Added - diff]
.gitignore[Added - diff]
LICENSE[Added - diff]
Makefile[Added - diff]
README.md[Added - diff]
def/RF.def[Added - diff]
def/user_proj_example.def[Added - diff]
def/user_project_wrapper.def.gz[Added - diff]
docs/Makefile[Added - diff]
docs/environment.yml[Added - diff]
docs/requirements.txt[Added - diff]
docs/source/_static/counter_32.png[Added - diff]
docs/source/_static/empty.png[Added - diff]
docs/source/_static/layout.png[Added - diff]
docs/source/_static/option1.png[Added - diff]
docs/source/_static/option2.png[Added - diff]
docs/source/_static/option3.png[Added - diff]
docs/source/_static/pitch.png[Added - diff]
docs/source/_static/wrapper.png[Added - diff]
docs/source/conf.py[Added - diff]
docs/source/index.rst[Added - diff]
docs/source/quickstart.rst[Added - diff]
gds/RF.gds.gz[Added - diff]
gds/user_proj_example.gds.gz[Added - diff]
gds/user_project_wrapper.gds.gz.00.split[Added - diff]
gds/user_project_wrapper.gds.gz.01.split[Added - diff]
lef/RF.lef[Added - diff]
lef/user_proj_example.lef[Added - diff]
lef/user_project_wrapper.lef[Added - diff]
lib/RF.lib[Added - diff]
lib/user_project_wrapper.lib[Added - diff]
mag/RF.mag[Added - diff]
mag/user_proj_example.mag[Added - diff]
mag/user_project_wrapper.mag.gz.00.split[Added - diff]
mag/user_project_wrapper.mag.gz.01.split[Added - diff]
maglef/RF.mag[Added - diff]
maglef/user_proj_example.mag[Added - diff]
maglef/user_project_wrapper.mag[Added - diff]
openlane/.gitignore[Added - diff]
openlane/Makefile[Added - diff]
openlane/rf/config.json[Added - diff]
openlane/rf/config.tcl[Added - diff]
openlane/rf/flow_it.tcl[Added - diff]
openlane/rf/macro_placement.cfg[Added - diff]
openlane/rf/pin_order.cfg[Added - diff]
openlane/rf/pow.def[Added - diff]
openlane/rf/pow.v[Added - diff]
openlane/user_proj_example/config.json[Added - diff]
openlane/user_proj_example/pin_order.cfg[Added - diff]
openlane/user_project_wrapper/config.json[Added - diff]
openlane/user_project_wrapper/config.tcl[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/default_wrapper_cfgs.tcl[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/fixed_wrapper_cfgs.tcl[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def[Added - diff]
openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def[Added - diff]
openlane/user_project_wrapper/macro.cfg[Added - diff]
openlane/user_project_wrapper/pin_order.cfg[Added - diff]
sdc/RF.sdc[Added - diff]
sdc/user_project_wrapper.sdc[Added - diff]
sdf/RF.sdf[Added - diff]
sdf/multicorner/max/user_project_wrapper.ff.sdf.gz[Added - diff]
sdf/multicorner/max/user_project_wrapper.ss.sdf.gz[Added - diff]
sdf/multicorner/max/user_project_wrapper.tt.sdf.gz[Added - diff]
sdf/multicorner/min/user_project_wrapper.ff.sdf.gz[Added - diff]
sdf/multicorner/min/user_project_wrapper.ss.sdf.gz[Added - diff]
sdf/multicorner/min/user_project_wrapper.tt.sdf.gz[Added - diff]
sdf/multicorner/nom/user_project_wrapper.ff.sdf.gz[Added - diff]
sdf/multicorner/nom/user_project_wrapper.ss.sdf.gz[Added - diff]
sdf/multicorner/nom/user_project_wrapper.tt.sdf.gz[Added - diff]
sdf/user_project_wrapper.sdf.gz[Added - diff]
signoff/user_proj_example/OPENLANE_VERSION[Added - diff]
signoff/user_proj_example/PDK_SOURCES[Added - diff]
signoff/user_project_wrapper/OPENLANE_VERSION[Added - diff]
signoff/user_project_wrapper/PDK_SOURCES[Added - diff]
spef/RF.spef[Added - diff]
spef/multicorner/user_project_wrapper.max.spef.gz.00.split[Added - diff]
spef/multicorner/user_project_wrapper.max.spef.gz.01.split[Added - diff]
spef/multicorner/user_project_wrapper.min.spef.gz.00.split[Added - diff]
spef/multicorner/user_project_wrapper.min.spef.gz.01.split[Added - diff]
spef/multicorner/user_project_wrapper.nom.spef.gz.00.split[Added - diff]
spef/multicorner/user_project_wrapper.nom.spef.gz.01.split[Added - diff]
spef/user_project_wrapper.spef.gz.00.split[Added - diff]
spef/user_project_wrapper.spef.gz.01.split[Added - diff]
spi/lvs/RF.spice[Added - diff]
spi/lvs/user_proj_example.spice[Added - diff]
spi/lvs/user_project_wrapper.spice[Added - diff]
verilog/dv/Makefile[Added - diff]
verilog/dv/README.md[Added - diff]
verilog/dv/core/Makefile[Added - diff]
verilog/dv/core/core.c[Added - diff]
verilog/dv/core/core_tb.v[Added - diff]
verilog/dv/io_ports/Makefile[Added - diff]
verilog/dv/io_ports/io_ports.c[Added - diff]
verilog/dv/io_ports/io_ports_tb.v[Added - diff]
verilog/dv/la_test1/Makefile[Added - diff]
verilog/dv/la_test1/la_test1.c[Added - diff]
verilog/dv/la_test1/la_test1_tb.v[Added - diff]
verilog/dv/la_test2/Makefile[Added - diff]
verilog/dv/la_test2/la_test2.c[Added - diff]
verilog/dv/la_test2/la_test2_tb.v[Added - diff]
verilog/dv/local-install.md[Added - diff]
verilog/dv/mprj_stimulus/Makefile[Added - diff]
verilog/dv/mprj_stimulus/mprj_stimulus.c[Added - diff]
verilog/dv/mprj_stimulus/mprj_stimulus_tb.v[Added - diff]
verilog/dv/primes/Makefile[Added - diff]
verilog/dv/primes/primes.c[Added - diff]
verilog/dv/primes/primes_tb.v[Added - diff]
verilog/dv/spi_gpio/Makefile[Added - diff]
verilog/dv/spi_gpio/spi_gpio.c[Added - diff]
verilog/dv/spi_gpio/spi_gpio_tb.v[Added - diff]
verilog/dv/wb_port/Makefile[Added - diff]
verilog/dv/wb_port/wb_port.c[Added - diff]
verilog/dv/wb_port/wb_port_tb.v[Added - diff]
verilog/gl/Adder.v[Added - diff]
verilog/gl/RF.nl.v[Added - diff]
verilog/gl/RF.v[Added - diff]
verilog/gl/RF_phy.v[Added - diff]
verilog/gl/hardfloat_wrapper.v[Added - diff]
verilog/gl/user_proj_example.v[Added - diff]
verilog/gl/user_project_wrapper.nl.v[Added - diff]
verilog/gl/user_project_wrapper.v.gz[Added - diff]
verilog/includes/includes.gl+sdf.caravel_user_project[Added - diff]
verilog/includes/includes.gl.caravel_user_project[Added - diff]
verilog/includes/includes.rtl.caravel_user_project[Added - diff]
verilog/rtl/AGU.v[Added - diff]
verilog/rtl/BranchHistoryTable.v[Added - diff]
verilog/rtl/BranchPredictionTable.v[Added - diff]
verilog/rtl/BranchPredictor.v[Added - diff]
verilog/rtl/BranchSelector.v[Added - diff]
verilog/rtl/BranchTargetBuffer.v[Added - diff]
verilog/rtl/BranchTargetBufferNew.v[Added - diff]
verilog/rtl/CacheController.v[Added - diff]
verilog/rtl/CacheTable.v[Added - diff]
verilog/rtl/ControlRegs.v[Added - diff]
verilog/rtl/Core.v[Added - diff]
verilog/rtl/Divide.v[Added - diff]
verilog/rtl/ExternalMemorySim.v[Added - diff]
verilog/rtl/FDiv.v[Added - diff]
verilog/rtl/FMul.v[Added - diff]
verilog/rtl/FPU.v[Added - diff]
verilog/rtl/Fuse.v[Added - diff]
verilog/rtl/ICacheTable.v[Added - diff]
verilog/rtl/Include.v[Added - diff]
verilog/rtl/IndirectBranchPredictor.v[Added - diff]
verilog/rtl/InstrDecoder.v[Added - diff]
verilog/rtl/IntALU.v[Added - diff]
verilog/rtl/IssueQueue.v[Added - diff]
verilog/rtl/LZCnt.v[Added - diff]
verilog/rtl/Load.v[Added - diff]
verilog/rtl/LoadBuffer.v[Added - diff]
verilog/rtl/LoadStoreUnit.v[Added - diff]
verilog/rtl/MemRTL.v[Added - diff]
verilog/rtl/MemoryController.v[Added - diff]
verilog/rtl/MemoryControllerSim.v[Added - diff]
verilog/rtl/Multiply.v[Added - diff]
verilog/rtl/MultiplySmall.v[Added - diff]
verilog/rtl/PCFile.v[Added - diff]
verilog/rtl/PopCnt.v[Added - diff]
verilog/rtl/PreDecode.v[Added - diff]
verilog/rtl/ProgramCounter.v[Added - diff]
verilog/rtl/RF.v[Added - diff]
verilog/rtl/RF_FP.v[Added - diff]
verilog/rtl/RF_phy.v[Added - diff]
verilog/rtl/ROB.v[Added - diff]
verilog/rtl/Rename.v[Added - diff]
verilog/rtl/RenameHistory.v[Added - diff]
verilog/rtl/RenameTable.v[Added - diff]
verilog/rtl/ReservationStation.v[Added - diff]
verilog/rtl/ReturnStack.v[Added - diff]
verilog/rtl/SRAMWrapper.v[Added - diff]
verilog/rtl/SRAMWrapperDC.v[Added - diff]
verilog/rtl/SRAMWrapperIC.v[Added - diff]
verilog/rtl/StoreAGU.v[Added - diff]
verilog/rtl/StoreQueue.v[Added - diff]
verilog/rtl/TagBuffer.v[Added - diff]
verilog/rtl/TagePredictor.v[Added - diff]
verilog/rtl/TageTable.v[Added - diff]
verilog/rtl/Top.v[Added - diff]
verilog/rtl/a.out[Added - diff]
verilog/rtl/adder_fa.v[Added - diff]
verilog/rtl/adder_rtl.v[Added - diff]
verilog/rtl/defines.v[Added - diff]
verilog/rtl/hardfloat/8086-SSE/HardFloat_specialize.v[Added - diff]
verilog/rtl/hardfloat/8086-SSE/HardFloat_specialize.vi[Added - diff]
verilog/rtl/hardfloat/ARM-VFPv2/HardFloat_specialize.v[Added - diff]
verilog/rtl/hardfloat/ARM-VFPv2/HardFloat_specialize.vi[Added - diff]
verilog/rtl/hardfloat/HardFloat_consts.vi[Added - diff]
verilog/rtl/hardfloat/HardFloat_localFuncs.vi[Added - diff]
verilog/rtl/hardfloat/HardFloat_primitives.v[Added - diff]
verilog/rtl/hardfloat/HardFloat_rawFN.v[Added - diff]
verilog/rtl/hardfloat/HardFloat_specialize.v[Added - diff]
verilog/rtl/hardfloat/HardFloat_specialize.vi[Added - diff]
verilog/rtl/hardfloat/addRecFN.v[Added - diff]
verilog/rtl/hardfloat/compareRecFN.v[Added - diff]
verilog/rtl/hardfloat/divSqrtRecFN_small.v[Added - diff]
verilog/rtl/hardfloat/fNToRecFN.v[Added - diff]
verilog/rtl/hardfloat/iNToRecFN.v[Added - diff]
verilog/rtl/hardfloat/isSigNaNRecFN.v[Added - diff]
verilog/rtl/hardfloat/mulAddRecFN.v[Added - diff]
verilog/rtl/hardfloat/mulRecFN.v[Added - diff]
verilog/rtl/hardfloat/recFNToFN.v[Added - diff]
verilog/rtl/hardfloat/recFNToIN.v[Added - diff]
verilog/rtl/hardfloat/recFNToRecFN.v[Added - diff]
verilog/rtl/hardfloat/synth_test.yosys[Added - diff]
verilog/rtl/hardfloat_wrapper.v[Added - diff]
verilog/rtl/register_file_test.v[Added - diff]
verilog/rtl/register_file_test_nodec.v[Added - diff]
verilog/rtl/sky130_sram_1kbyte_1rw1r_32x256_8.v[Added - diff]
verilog/rtl/sky130_sram_2kbyte_1rw1r_32x512_8_2.v[Added - diff]
verilog/rtl/sky130_sram_8kbyte_1rw1r_32x2048_8.v[Added - diff]
verilog/rtl/sky130_sram_8kbyte_1rw_64x1024_8.v[Added - diff]
verilog/rtl/soomrv.v[Added - diff]
verilog/rtl/soomrv.v.old[Added - diff]
verilog/rtl/soomrv2.v[Added - diff]
verilog/rtl/uprj_netlists.v[Added - diff]
verilog/rtl/user_defines.v[Added - diff]
verilog/rtl/user_proj_example.v[Added - diff]
verilog/rtl/user_project_wrapper.v[Added - diff]
verilog/rtl/user_project_wrapper.v.new[Added - diff]
verilog/rtl/user_project_wrapper.v.old[Added - diff]

220 files changed

tree: 92767a0278d68a6a71e49a0379c8cab9d9a2f627

README.md

Caravel User Project

:exclamation: Important Note

Please fill in your project documentation in this README.md file

Refer to README for a quickstart of how to use caravel_user_project

Refer to README for this sample project documentation.