| #! /usr/bin/vvp |
| :ivl_version "11.0 (stable)" "(v11_0)"; |
| :ivl_delay_selection "TYPICAL"; |
| :vpi_time_precision + 0; |
| :vpi_module "/usr/lib/ivl/system.vpi"; |
| :vpi_module "/usr/lib/ivl/vhdl_sys.vpi"; |
| :vpi_module "/usr/lib/ivl/vhdl_textio.vpi"; |
| :vpi_module "/usr/lib/ivl/v2005_math.vpi"; |
| :vpi_module "/usr/lib/ivl/va_math.vpi"; |
| S_0x555ec06b44c0 .scope module, "SRAMWrapper" "SRAMWrapper" 2 1; |
| .timescale 0 0; |
| .port_info 0 /INPUT 1 "clk"; |
| .port_info 1 /INPUT 1 "nce0"; |
| .port_info 2 /INPUT 1 "nwe0"; |
| .port_info 3 /INPUT 10 "addr0"; |
| .port_info 4 /INPUT 32 "wdata0"; |
| .port_info 5 /INPUT 4 "wmask0"; |
| .port_info 6 /OUTPUT 32 "rdata0"; |
| .port_info 7 /INPUT 1 "nce1"; |
| .port_info 8 /INPUT 10 "addr1"; |
| .port_info 9 /OUTPUT 32 "rdata1"; |
| P_0x555ec0715380 .param/l "ADDR_LEN" 0 2 5, +C4<00000000000000000000000000001010>; |
| P_0x555ec07153c0 .param/l "LENGTH" 1 2 21, +C4<00000000000000000000000000000010>; |
| P_0x555ec0715400 .param/l "SIZE_IN_WORDS" 0 2 3, +C4<00000000000000000000010000000000>; |
| P_0x555ec0715440 .param/l "WIDTH" 1 2 22, +C4<00000000000000000000000000000001>; |
| P_0x555ec0715480 .param/l "WORD_SIZE" 0 2 4, +C4<00000000000000000000000000100000>; |
| o0x7f6577b00f18 .functor BUFZ 10, C4<zzzzzzzzzz>; HiZ drive |
| v0x555ec0739030_0 .net "addr0", 9 0, o0x7f6577b00f18; 0 drivers |
| o0x7f6577b00f48 .functor BUFZ 10, C4<zzzzzzzzzz>; HiZ drive |
| v0x555ec0739130_0 .net "addr1", 9 0, o0x7f6577b00f48; 0 drivers |
| o0x7f6577b000d8 .functor BUFZ 1, C4<z>; HiZ drive |
| v0x555ec0739210_0 .net "clk", 0 0, o0x7f6577b000d8; 0 drivers |
| v0x555ec0739340_0 .var "lastAddr0", 9 0; |
| v0x555ec0739400_0 .var "lastAddr1", 9 0; |
| v0x555ec07394e0_0 .var "lastRe0", 0 0; |
| v0x555ec07395a0_0 .var "lastRe1", 0 0; |
| o0x7f6577b01038 .functor BUFZ 1, C4<z>; HiZ drive |
| v0x555ec0739660_0 .net "nce0", 0 0, o0x7f6577b01038; 0 drivers |
| o0x7f6577b01068 .functor BUFZ 1, C4<z>; HiZ drive |
| v0x555ec0739720_0 .net "nce1", 0 0, o0x7f6577b01068; 0 drivers |
| o0x7f6577b00288 .functor BUFZ 1, C4<z>; HiZ drive |
| v0x555ec0739870_0 .net "nwe0", 0 0, o0x7f6577b00288; 0 drivers |
| v0x555ec0739910_0 .var "rdata0", 31 0; |
| v0x555ec07399f0_0 .var "rdata1", 31 0; |
| v0x555ec0739ad0_0 .net "readData0", 63 0, L_0x555ec073b5b0; 1 drivers |
| v0x555ec0739b90_0 .net "readData1", 63 0, L_0x555ec073bde0; 1 drivers |
| o0x7f6577b001c8 .functor BUFZ 32, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive |
| v0x555ec0739c50_0 .net "wdata0", 31 0, o0x7f6577b001c8; 0 drivers |
| o0x7f6577b002e8 .functor BUFZ 4, C4<zzzz>; HiZ drive |
| v0x555ec0739d10_0 .net "wmask0", 3 0, o0x7f6577b002e8; 0 drivers |
| L_0x555ec073a000 .part o0x7f6577b00f18, 9, 1; |
| L_0x555ec073a5a0 .part o0x7f6577b00f18, 0, 9; |
| L_0x555ec073a730 .part o0x7f6577b00f48, 9, 1; |
| L_0x555ec073ad00 .part o0x7f6577b00f48, 0, 9; |
| L_0x555ec073af10 .part o0x7f6577b00f18, 9, 1; |
| L_0x555ec073b440 .part o0x7f6577b00f18, 0, 9; |
| L_0x555ec073b5b0 .concat8 [ 32 32 0 0], v0x555ec0734980_0, v0x555ec0737c40_0; |
| L_0x555ec073b6f0 .part o0x7f6577b00f48, 9, 1; |
| L_0x555ec073bcb0 .part o0x7f6577b00f48, 0, 9; |
| L_0x555ec073bde0 .concat8 [ 32 32 0 0], v0x555ec0734a60_0, v0x555ec0737d20_0; |
| S_0x555ec06b4020 .scope generate, "genblk1" "genblk1" 2 36, 2 36 0, S_0x555ec06b44c0; |
| .timescale 0 0; |
| E_0x555ec06ed250 .event posedge, v0x555ec0706800_0; |
| S_0x555ec06b53a0 .scope generate, "genblk3[0]" "genblk3[0]" 2 70, 2 70 0, S_0x555ec06b44c0; |
| .timescale 0 0; |
| P_0x555ec0713680 .param/l "i" 0 2 70, +C4<00>; |
| S_0x555ec06f9830 .scope generate, "genblk4[0]" "genblk4[0]" 2 71, 2 71 0, S_0x555ec06b53a0; |
| .timescale 0 0; |
| P_0x555ec06f9a10 .param/l "j" 0 2 71, +C4<00>; |
| S_0x555ec06f9ab0 .scope generate, "genblk6" "genblk6" 2 73, 2 73 0, S_0x555ec06f9830; |
| .timescale 0 0; |
| L_0x555ec07105f0 .functor AND 1, L_0x555ec0739f60, L_0x555ec073a270, C4<1>, C4<1>; |
| L_0x555ec0710c00 .functor AND 1, L_0x555ec073a690, L_0x555ec073a9b0, C4<1>, C4<1>; |
| v0x555ec07351b0_0 .net *"_ivl_1", 0 0, L_0x555ec0739f60; 1 drivers |
| v0x555ec0735290_0 .net *"_ivl_12", 0 0, L_0x555ec07105f0; 1 drivers |
| v0x555ec0735350_0 .net *"_ivl_17", 0 0, L_0x555ec073a690; 1 drivers |
| v0x555ec07353f0_0 .net *"_ivl_18", 0 0, L_0x555ec073a730; 1 drivers |
| v0x555ec07354d0_0 .net *"_ivl_19", 2 0, L_0x555ec073a800; 1 drivers |
| v0x555ec07355b0_0 .net *"_ivl_2", 0 0, L_0x555ec073a000; 1 drivers |
| L_0x7f6577ab70a8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; |
| v0x555ec0735690_0 .net *"_ivl_22", 1 0, L_0x7f6577ab70a8; 1 drivers |
| L_0x7f6577ab70f0 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>; |
| v0x555ec0735770_0 .net/2u *"_ivl_23", 2 0, L_0x7f6577ab70f0; 1 drivers |
| v0x555ec0735850_0 .net *"_ivl_25", 0 0, L_0x555ec073a9b0; 1 drivers |
| v0x555ec0735910_0 .net *"_ivl_28", 0 0, L_0x555ec0710c00; 1 drivers |
| v0x555ec07359d0_0 .net *"_ivl_3", 2 0, L_0x555ec073a100; 1 drivers |
| L_0x7f6577ab7018 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; |
| v0x555ec0735ab0_0 .net *"_ivl_6", 1 0, L_0x7f6577ab7018; 1 drivers |
| L_0x7f6577ab7060 .functor BUFT 1, C4<000>, C4<0>, C4<0>, C4<0>; |
| v0x555ec0735b90_0 .net/2u *"_ivl_7", 2 0, L_0x7f6577ab7060; 1 drivers |
| v0x555ec0735c70_0 .net *"_ivl_9", 0 0, L_0x555ec073a270; 1 drivers |
| L_0x555ec0739f60 .reduce/nor o0x7f6577b01038; |
| L_0x555ec073a100 .concat [ 1 2 0 0], L_0x555ec073a000, L_0x7f6577ab7018; |
| L_0x555ec073a270 .cmp/eq 3, L_0x555ec073a100, L_0x7f6577ab7060; |
| L_0x555ec073a480 .reduce/nor L_0x555ec07105f0; |
| L_0x555ec073a690 .reduce/nor o0x7f6577b01068; |
| L_0x555ec073a800 .concat [ 1 2 0 0], L_0x555ec073a730, L_0x7f6577ab70a8; |
| L_0x555ec073a9b0 .cmp/eq 3, L_0x555ec073a800, L_0x7f6577ab70f0; |
| L_0x555ec073abc0 .reduce/nor L_0x555ec0710c00; |
| S_0x555ec06c6750 .scope module, "sram" "sky130_sram_2kbyte_1rw1r_32x512_8" 2 90, 3 6 0, S_0x555ec06f9ab0; |
| .timescale 0 0; |
| .port_info 0 /INPUT 1 "clk0"; |
| .port_info 1 /INPUT 1 "csb0"; |
| .port_info 2 /INPUT 1 "web0"; |
| .port_info 3 /INPUT 4 "wmask0"; |
| .port_info 4 /INPUT 9 "addr0"; |
| .port_info 5 /INPUT 32 "din0"; |
| .port_info 6 /OUTPUT 32 "dout0"; |
| .port_info 7 /INPUT 1 "clk1"; |
| .port_info 8 /INPUT 1 "csb1"; |
| .port_info 9 /INPUT 9 "addr1"; |
| .port_info 10 /OUTPUT 32 "dout1"; |
| P_0x555ec06c6930 .param/l "ADDR_WIDTH" 0 3 19, +C4<00000000000000000000000000001001>; |
| P_0x555ec06c6970 .param/l "DATA_WIDTH" 0 3 18, +C4<00000000000000000000000000100000>; |
| P_0x555ec06c69b0 .param/l "DELAY" 0 3 22, +C4<00000000000000000000000000000011>; |
| P_0x555ec06c69f0 .param/l "NUM_WMASKS" 0 3 17, +C4<00000000000000000000000000000100>; |
| P_0x555ec06c6a30 .param/l "RAM_DEPTH" 0 3 20, +C4<00000000000000000000000000000001000000000>; |
| P_0x555ec06c6a70 .param/l "T_HOLD" 0 3 24, +C4<00000000000000000000000000000001>; |
| P_0x555ec06c6ab0 .param/l "VERBOSE" 0 3 23, +C4<00000000000000000000000000000001>; |
| v0x555ec0711350_0 .net "addr0", 8 0, L_0x555ec073a5a0; 1 drivers |
| v0x555ec06e7740_0 .var "addr0_reg", 8 0; |
| v0x555ec06e9920_0 .net "addr1", 8 0, L_0x555ec073ad00; 1 drivers |
| v0x555ec06eb010_0 .var "addr1_reg", 8 0; |
| v0x555ec0706800_0 .net "clk0", 0 0, o0x7f6577b000d8; alias, 0 drivers |
| v0x555ec07156e0_0 .net "clk1", 0 0, o0x7f6577b000d8; alias, 0 drivers |
| v0x555ec070b630_0 .net "csb0", 0 0, L_0x555ec073a480; 1 drivers |
| v0x555ec0734580_0 .var "csb0_reg", 0 0; |
| v0x555ec0734640_0 .net "csb1", 0 0, L_0x555ec073abc0; 1 drivers |
| v0x555ec0734700_0 .var "csb1_reg", 0 0; |
| v0x555ec07347c0_0 .net "din0", 31 0, o0x7f6577b001c8; alias, 0 drivers |
| v0x555ec07348a0_0 .var "din0_reg", 31 0; |
| v0x555ec0734980_0 .var "dout0", 31 0; |
| v0x555ec0734a60_0 .var "dout1", 31 0; |
| v0x555ec0734b40 .array "mem", 511 0, 31 0; |
| v0x555ec0734c00_0 .net "web0", 0 0, o0x7f6577b00288; alias, 0 drivers |
| v0x555ec0734cc0_0 .var "web0_reg", 0 0; |
| v0x555ec0734e90_0 .net "wmask0", 3 0, o0x7f6577b002e8; alias, 0 drivers |
| v0x555ec0734f70_0 .var "wmask0_reg", 3 0; |
| E_0x555ec06eeb20 .event negedge, v0x555ec0706800_0; |
| S_0x555ec0715e40 .scope begin, "MEM_READ0" "MEM_READ0" 3 101, 3 101 0, S_0x555ec06c6750; |
| .timescale 0 0; |
| S_0x555ec0715fd0 .scope begin, "MEM_READ1" "MEM_READ1" 3 109, 3 109 0, S_0x555ec06c6750; |
| .timescale 0 0; |
| S_0x555ec0716160 .scope begin, "MEM_WRITE0" "MEM_WRITE0" 3 85, 3 85 0, S_0x555ec06c6750; |
| .timescale 0 0; |
| S_0x555ec0735d30 .scope generate, "genblk3[1]" "genblk3[1]" 2 70, 2 70 0, S_0x555ec06b44c0; |
| .timescale 0 0; |
| P_0x555ec0735ee0 .param/l "i" 0 2 70, +C4<01>; |
| S_0x555ec0735fa0 .scope generate, "genblk4[0]" "genblk4[0]" 2 71, 2 71 0, S_0x555ec0735d30; |
| .timescale 0 0; |
| P_0x555ec07361a0 .param/l "j" 0 2 71, +C4<00>; |
| S_0x555ec0736280 .scope generate, "genblk6" "genblk6" 2 73, 2 73 0, S_0x555ec0735fa0; |
| .timescale 0 0; |
| L_0x555ec0711230 .functor AND 1, L_0x555ec073ae20, L_0x555ec073b140, C4<1>, C4<1>; |
| L_0x555ec06e7680 .functor AND 1, L_0x555ec073b650, L_0x555ec073b990, C4<1>, C4<1>; |
| v0x555ec0738480_0 .net *"_ivl_1", 0 0, L_0x555ec073ae20; 1 drivers |
| v0x555ec0738560_0 .net *"_ivl_12", 0 0, L_0x555ec0711230; 1 drivers |
| v0x555ec0738620_0 .net *"_ivl_17", 0 0, L_0x555ec073b650; 1 drivers |
| v0x555ec07386f0_0 .net *"_ivl_18", 0 0, L_0x555ec073b6f0; 1 drivers |
| v0x555ec07387d0_0 .net *"_ivl_19", 2 0, L_0x555ec073b7e0; 1 drivers |
| v0x555ec07388b0_0 .net *"_ivl_2", 0 0, L_0x555ec073af10; 1 drivers |
| L_0x7f6577ab71c8 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; |
| v0x555ec0738990_0 .net *"_ivl_22", 1 0, L_0x7f6577ab71c8; 1 drivers |
| L_0x7f6577ab7210 .functor BUFT 1, C4<001>, C4<0>, C4<0>, C4<0>; |
| v0x555ec0738a70_0 .net/2u *"_ivl_23", 2 0, L_0x7f6577ab7210; 1 drivers |
| v0x555ec0738b50_0 .net *"_ivl_25", 0 0, L_0x555ec073b990; 1 drivers |
| v0x555ec0738c10_0 .net *"_ivl_28", 0 0, L_0x555ec06e7680; 1 drivers |
| v0x555ec0738cd0_0 .net *"_ivl_3", 2 0, L_0x555ec073afb0; 1 drivers |
| L_0x7f6577ab7138 .functor BUFT 1, C4<00>, C4<0>, C4<0>, C4<0>; |
| v0x555ec0738db0_0 .net *"_ivl_6", 1 0, L_0x7f6577ab7138; 1 drivers |
| L_0x7f6577ab7180 .functor BUFT 1, C4<001>, C4<0>, C4<0>, C4<0>; |
| v0x555ec0738e90_0 .net/2u *"_ivl_7", 2 0, L_0x7f6577ab7180; 1 drivers |
| v0x555ec0738f70_0 .net *"_ivl_9", 0 0, L_0x555ec073b140; 1 drivers |
| L_0x555ec073ae20 .reduce/nor o0x7f6577b01038; |
| L_0x555ec073afb0 .concat [ 1 2 0 0], L_0x555ec073af10, L_0x7f6577ab7138; |
| L_0x555ec073b140 .cmp/eq 3, L_0x555ec073afb0, L_0x7f6577ab7180; |
| L_0x555ec073b320 .reduce/nor L_0x555ec0711230; |
| L_0x555ec073b650 .reduce/nor o0x7f6577b01068; |
| L_0x555ec073b7e0 .concat [ 1 2 0 0], L_0x555ec073b6f0, L_0x7f6577ab71c8; |
| L_0x555ec073b990 .cmp/eq 3, L_0x555ec073b7e0, L_0x7f6577ab7210; |
| L_0x555ec073bb70 .reduce/nor L_0x555ec06e7680; |
| S_0x555ec0736460 .scope module, "sram" "sky130_sram_2kbyte_1rw1r_32x512_8" 2 90, 3 6 0, S_0x555ec0736280; |
| .timescale 0 0; |
| .port_info 0 /INPUT 1 "clk0"; |
| .port_info 1 /INPUT 1 "csb0"; |
| .port_info 2 /INPUT 1 "web0"; |
| .port_info 3 /INPUT 4 "wmask0"; |
| .port_info 4 /INPUT 9 "addr0"; |
| .port_info 5 /INPUT 32 "din0"; |
| .port_info 6 /OUTPUT 32 "dout0"; |
| .port_info 7 /INPUT 1 "clk1"; |
| .port_info 8 /INPUT 1 "csb1"; |
| .port_info 9 /INPUT 9 "addr1"; |
| .port_info 10 /OUTPUT 32 "dout1"; |
| P_0x555ec0736660 .param/l "ADDR_WIDTH" 0 3 19, +C4<00000000000000000000000000001001>; |
| P_0x555ec07366a0 .param/l "DATA_WIDTH" 0 3 18, +C4<00000000000000000000000000100000>; |
| P_0x555ec07366e0 .param/l "DELAY" 0 3 22, +C4<00000000000000000000000000000011>; |
| P_0x555ec0736720 .param/l "NUM_WMASKS" 0 3 17, +C4<00000000000000000000000000000100>; |
| P_0x555ec0736760 .param/l "RAM_DEPTH" 0 3 20, +C4<00000000000000000000000000000001000000000>; |
| P_0x555ec07367a0 .param/l "T_HOLD" 0 3 24, +C4<00000000000000000000000000000001>; |
| P_0x555ec07367e0 .param/l "VERBOSE" 0 3 23, +C4<00000000000000000000000000000001>; |
| v0x555ec0737270_0 .net "addr0", 8 0, L_0x555ec073b440; 1 drivers |
| v0x555ec0737330_0 .var "addr0_reg", 8 0; |
| v0x555ec0737410_0 .net "addr1", 8 0, L_0x555ec073bcb0; 1 drivers |
| v0x555ec0737500_0 .var "addr1_reg", 8 0; |
| v0x555ec07375e0_0 .net "clk0", 0 0, o0x7f6577b000d8; alias, 0 drivers |
| v0x555ec0737720_0 .net "clk1", 0 0, o0x7f6577b000d8; alias, 0 drivers |
| v0x555ec07377c0_0 .net "csb0", 0 0, L_0x555ec073b320; 1 drivers |
| v0x555ec0737880_0 .var "csb0_reg", 0 0; |
| v0x555ec0737940_0 .net "csb1", 0 0, L_0x555ec073bb70; 1 drivers |
| v0x555ec0737a00_0 .var "csb1_reg", 0 0; |
| v0x555ec0737ac0_0 .net "din0", 31 0, o0x7f6577b001c8; alias, 0 drivers |
| v0x555ec0737b80_0 .var "din0_reg", 31 0; |
| v0x555ec0737c40_0 .var "dout0", 31 0; |
| v0x555ec0737d20_0 .var "dout1", 31 0; |
| v0x555ec0737e00 .array "mem", 511 0, 31 0; |
| v0x555ec0737ec0_0 .net "web0", 0 0, o0x7f6577b00288; alias, 0 drivers |
| v0x555ec0737f60_0 .var "web0_reg", 0 0; |
| v0x555ec0738110_0 .net "wmask0", 3 0, o0x7f6577b002e8; alias, 0 drivers |
| v0x555ec0738200_0 .var "wmask0_reg", 3 0; |
| S_0x555ec0736c60 .scope begin, "MEM_READ0" "MEM_READ0" 3 101, 3 101 0, S_0x555ec0736460; |
| .timescale 0 0; |
| S_0x555ec0736e60 .scope begin, "MEM_READ1" "MEM_READ1" 3 109, 3 109 0, S_0x555ec0736460; |
| .timescale 0 0; |
| S_0x555ec0737060 .scope begin, "MEM_WRITE0" "MEM_WRITE0" 3 85, 3 85 0, S_0x555ec0736460; |
| .timescale 0 0; |
| .scope S_0x555ec06b4020; |
| T_0 ; |
| %wait E_0x555ec06ed250; |
| %load/vec4 v0x555ec0739030_0; |
| %assign/vec4 v0x555ec0739340_0, 0; |
| %load/vec4 v0x555ec0739130_0; |
| %assign/vec4 v0x555ec0739400_0, 0; |
| %load/vec4 v0x555ec0739660_0; |
| %nor/r; |
| %load/vec4 v0x555ec0739870_0; |
| %and; |
| %assign/vec4 v0x555ec07394e0_0, 0; |
| %load/vec4 v0x555ec0739720_0; |
| %nor/r; |
| %assign/vec4 v0x555ec07395a0_0, 0; |
| %load/vec4 v0x555ec07394e0_0; |
| %nor/r; |
| %flag_set/vec4 8; |
| %jmp/0xz T_0.0, 8; |
| %load/vec4 v0x555ec0739ad0_0; |
| %load/vec4 v0x555ec0739340_0; |
| %parti/s 1, 9, 5; |
| %pad/u 6; |
| %muli 32, 0, 6; |
| %part/u 32; |
| %assign/vec4 v0x555ec0739910_0, 0; |
| T_0.0 ; |
| %load/vec4 v0x555ec07395a0_0; |
| %nor/r; |
| %flag_set/vec4 8; |
| %jmp/0xz T_0.2, 8; |
| %load/vec4 v0x555ec0739b90_0; |
| %load/vec4 v0x555ec0739400_0; |
| %parti/s 1, 9, 5; |
| %pad/u 6; |
| %muli 32, 0, 6; |
| %part/u 32; |
| %assign/vec4 v0x555ec07399f0_0, 0; |
| T_0.2 ; |
| %jmp T_0; |
| .thread T_0; |
| .scope S_0x555ec06c6750; |
| T_1 ; |
| %wait E_0x555ec06ed250; |
| %load/vec4 v0x555ec070b630_0; |
| %store/vec4 v0x555ec0734580_0, 0, 1; |
| %load/vec4 v0x555ec0734c00_0; |
| %store/vec4 v0x555ec0734cc0_0, 0, 1; |
| %load/vec4 v0x555ec0734e90_0; |
| %store/vec4 v0x555ec0734f70_0, 0, 4; |
| %load/vec4 v0x555ec0711350_0; |
| %store/vec4 v0x555ec06e7740_0, 0, 9; |
| %load/vec4 v0x555ec07347c0_0; |
| %store/vec4 v0x555ec07348a0_0, 0, 32; |
| %delay 1, 0; |
| %pushi/vec4 4294967295, 4294967295, 32; |
| %store/vec4 v0x555ec0734980_0, 0, 32; |
| %load/vec4 v0x555ec0734580_0; |
| %nor/r; |
| %load/vec4 v0x555ec0734cc0_0; |
| %and; |
| %pushi/vec4 1, 0, 1; |
| %and; |
| %flag_set/vec4 8; |
| %jmp/0xz T_1.0, 8; |
| %load/vec4 v0x555ec06e7740_0; |
| %pad/u 11; |
| %ix/vec4 4; |
| %load/vec4a v0x555ec0734b40, 4; |
| %vpi_call 3 59 "$display", $time, " Reading %m addr0=%b dout0=%b", v0x555ec06e7740_0, S<0,vec4,u32> {1 0 0}; |
| T_1.0 ; |
| %load/vec4 v0x555ec0734580_0; |
| %nor/r; |
| %load/vec4 v0x555ec0734cc0_0; |
| %nor/r; |
| %and; |
| %pushi/vec4 1, 0, 1; |
| %and; |
| %flag_set/vec4 8; |
| %jmp/0xz T_1.2, 8; |
| %vpi_call 3 61 "$display", $time, " Writing %m addr0=%b din0=%b wmask0=%b", v0x555ec06e7740_0, v0x555ec07348a0_0, v0x555ec0734f70_0 {0 0 0}; |
| T_1.2 ; |
| %jmp T_1; |
| .thread T_1; |
| .scope S_0x555ec06c6750; |
| T_2 ; |
| %wait E_0x555ec06ed250; |
| %load/vec4 v0x555ec0734640_0; |
| %store/vec4 v0x555ec0734700_0, 0, 1; |
| %load/vec4 v0x555ec06e9920_0; |
| %store/vec4 v0x555ec06eb010_0, 0, 9; |
| %load/vec4 v0x555ec070b630_0; |
| %nor/r; |
| %load/vec4 v0x555ec0734c00_0; |
| %nor/r; |
| %and; |
| %load/vec4 v0x555ec0734640_0; |
| %nor/r; |
| %and; |
| %load/vec4 v0x555ec0711350_0; |
| %load/vec4 v0x555ec06e9920_0; |
| %cmp/e; |
| %flag_get/vec4 4; |
| %and; |
| %flag_set/vec4 8; |
| %jmp/0xz T_2.0, 8; |
| %vpi_call 3 74 "$display", $time, " WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!", v0x555ec0711350_0, v0x555ec06e9920_0 {0 0 0}; |
| T_2.0 ; |
| %delay 1, 0; |
| %pushi/vec4 4294967295, 4294967295, 32; |
| %store/vec4 v0x555ec0734a60_0, 0, 32; |
| %load/vec4 v0x555ec0734700_0; |
| %nor/r; |
| %pushi/vec4 1, 0, 1; |
| %and; |
| %flag_set/vec4 8; |
| %jmp/0xz T_2.2, 8; |
| %load/vec4 v0x555ec06eb010_0; |
| %pad/u 11; |
| %ix/vec4 4; |
| %load/vec4a v0x555ec0734b40, 4; |
| %vpi_call 3 77 "$display", $time, " Reading %m addr1=%b dout1=%b", v0x555ec06eb010_0, S<0,vec4,u32> {1 0 0}; |
| T_2.2 ; |
| %jmp T_2; |
| .thread T_2; |
| .scope S_0x555ec06c6750; |
| T_3 ; |
| %wait E_0x555ec06eeb20; |
| %fork t_1, S_0x555ec0716160; |
| %jmp t_0; |
| .scope S_0x555ec0716160; |
| t_1 ; |
| %load/vec4 v0x555ec0734580_0; |
| %nor/r; |
| %load/vec4 v0x555ec0734cc0_0; |
| %nor/r; |
| %and; |
| %flag_set/vec4 8; |
| %jmp/0xz T_3.0, 8; |
| %load/vec4 v0x555ec0734f70_0; |
| %parti/s 1, 0, 2; |
| %flag_set/vec4 8; |
| %jmp/0xz T_3.2, 8; |
| %load/vec4 v0x555ec07348a0_0; |
| %parti/s 8, 0, 2; |
| %load/vec4 v0x555ec06e7740_0; |
| %pad/u 11; |
| %ix/vec4 4; |
| %flag_mov 8, 4; |
| %ix/load 5, 0, 0; |
| %flag_set/imm 4, 0; |
| %flag_or 4, 8; |
| %store/vec4a v0x555ec0734b40, 4, 5; |
| T_3.2 ; |
| %load/vec4 v0x555ec0734f70_0; |
| %parti/s 1, 1, 2; |
| %flag_set/vec4 8; |
| %jmp/0xz T_3.4, 8; |
| %load/vec4 v0x555ec07348a0_0; |
| %parti/s 8, 8, 5; |
| %load/vec4 v0x555ec06e7740_0; |
| %pad/u 11; |
| %ix/vec4 4; |
| %flag_mov 8, 4; |
| %ix/load 5, 8, 0; |
| %flag_set/imm 4, 0; |
| %flag_or 4, 8; |
| %store/vec4a v0x555ec0734b40, 4, 5; |
| T_3.4 ; |
| %load/vec4 v0x555ec0734f70_0; |
| %parti/s 1, 2, 3; |
| %flag_set/vec4 8; |
| %jmp/0xz T_3.6, 8; |
| %load/vec4 v0x555ec07348a0_0; |
| %parti/s 8, 16, 6; |
| %load/vec4 v0x555ec06e7740_0; |
| %pad/u 11; |
| %ix/vec4 4; |
| %flag_mov 8, 4; |
| %ix/load 5, 16, 0; |
| %flag_set/imm 4, 0; |
| %flag_or 4, 8; |
| %store/vec4a v0x555ec0734b40, 4, 5; |
| T_3.6 ; |
| %load/vec4 v0x555ec0734f70_0; |
| %parti/s 1, 3, 3; |
| %flag_set/vec4 8; |
| %jmp/0xz T_3.8, 8; |
| %load/vec4 v0x555ec07348a0_0; |
| %parti/s 8, 24, 6; |
| %load/vec4 v0x555ec06e7740_0; |
| %pad/u 11; |
| %ix/vec4 4; |
| %flag_mov 8, 4; |
| %ix/load 5, 24, 0; |
| %flag_set/imm 4, 0; |
| %flag_or 4, 8; |
| %store/vec4a v0x555ec0734b40, 4, 5; |
| T_3.8 ; |
| T_3.0 ; |
| %end; |
| .scope S_0x555ec06c6750; |
| t_0 %join; |
| %jmp T_3; |
| .thread T_3; |
| .scope S_0x555ec06c6750; |
| T_4 ; |
| %wait E_0x555ec06eeb20; |
| %fork t_3, S_0x555ec0715e40; |
| %jmp t_2; |
| .scope S_0x555ec0715e40; |
| t_3 ; |
| %load/vec4 v0x555ec0734580_0; |
| %nor/r; |
| %load/vec4 v0x555ec0734cc0_0; |
| %and; |
| %flag_set/vec4 8; |
| %jmp/0xz T_4.0, 8; |
| %load/vec4 v0x555ec06e7740_0; |
| %pad/u 11; |
| %ix/vec4 4; |
| %load/vec4a v0x555ec0734b40, 4; |
| %assign/vec4 v0x555ec0734980_0, 3; |
| T_4.0 ; |
| %end; |
| .scope S_0x555ec06c6750; |
| t_2 %join; |
| %jmp T_4; |
| .thread T_4; |
| .scope S_0x555ec06c6750; |
| T_5 ; |
| %wait E_0x555ec06eeb20; |
| %fork t_5, S_0x555ec0715fd0; |
| %jmp t_4; |
| .scope S_0x555ec0715fd0; |
| t_5 ; |
| %load/vec4 v0x555ec0734700_0; |
| %nor/r; |
| %flag_set/vec4 8; |
| %jmp/0xz T_5.0, 8; |
| %load/vec4 v0x555ec06eb010_0; |
| %pad/u 11; |
| %ix/vec4 4; |
| %load/vec4a v0x555ec0734b40, 4; |
| %assign/vec4 v0x555ec0734a60_0, 3; |
| T_5.0 ; |
| %end; |
| .scope S_0x555ec06c6750; |
| t_4 %join; |
| %jmp T_5; |
| .thread T_5; |
| .scope S_0x555ec0736460; |
| T_6 ; |
| %wait E_0x555ec06ed250; |
| %load/vec4 v0x555ec07377c0_0; |
| %store/vec4 v0x555ec0737880_0, 0, 1; |
| %load/vec4 v0x555ec0737ec0_0; |
| %store/vec4 v0x555ec0737f60_0, 0, 1; |
| %load/vec4 v0x555ec0738110_0; |
| %store/vec4 v0x555ec0738200_0, 0, 4; |
| %load/vec4 v0x555ec0737270_0; |
| %store/vec4 v0x555ec0737330_0, 0, 9; |
| %load/vec4 v0x555ec0737ac0_0; |
| %store/vec4 v0x555ec0737b80_0, 0, 32; |
| %delay 1, 0; |
| %pushi/vec4 4294967295, 4294967295, 32; |
| %store/vec4 v0x555ec0737c40_0, 0, 32; |
| %load/vec4 v0x555ec0737880_0; |
| %nor/r; |
| %load/vec4 v0x555ec0737f60_0; |
| %and; |
| %pushi/vec4 1, 0, 1; |
| %and; |
| %flag_set/vec4 8; |
| %jmp/0xz T_6.0, 8; |
| %load/vec4 v0x555ec0737330_0; |
| %pad/u 11; |
| %ix/vec4 4; |
| %load/vec4a v0x555ec0737e00, 4; |
| %vpi_call 3 59 "$display", $time, " Reading %m addr0=%b dout0=%b", v0x555ec0737330_0, S<0,vec4,u32> {1 0 0}; |
| T_6.0 ; |
| %load/vec4 v0x555ec0737880_0; |
| %nor/r; |
| %load/vec4 v0x555ec0737f60_0; |
| %nor/r; |
| %and; |
| %pushi/vec4 1, 0, 1; |
| %and; |
| %flag_set/vec4 8; |
| %jmp/0xz T_6.2, 8; |
| %vpi_call 3 61 "$display", $time, " Writing %m addr0=%b din0=%b wmask0=%b", v0x555ec0737330_0, v0x555ec0737b80_0, v0x555ec0738200_0 {0 0 0}; |
| T_6.2 ; |
| %jmp T_6; |
| .thread T_6; |
| .scope S_0x555ec0736460; |
| T_7 ; |
| %wait E_0x555ec06ed250; |
| %load/vec4 v0x555ec0737940_0; |
| %store/vec4 v0x555ec0737a00_0, 0, 1; |
| %load/vec4 v0x555ec0737410_0; |
| %store/vec4 v0x555ec0737500_0, 0, 9; |
| %load/vec4 v0x555ec07377c0_0; |
| %nor/r; |
| %load/vec4 v0x555ec0737ec0_0; |
| %nor/r; |
| %and; |
| %load/vec4 v0x555ec0737940_0; |
| %nor/r; |
| %and; |
| %load/vec4 v0x555ec0737270_0; |
| %load/vec4 v0x555ec0737410_0; |
| %cmp/e; |
| %flag_get/vec4 4; |
| %and; |
| %flag_set/vec4 8; |
| %jmp/0xz T_7.0, 8; |
| %vpi_call 3 74 "$display", $time, " WARNING: Writing and reading addr0=%b and addr1=%b simultaneously!", v0x555ec0737270_0, v0x555ec0737410_0 {0 0 0}; |
| T_7.0 ; |
| %delay 1, 0; |
| %pushi/vec4 4294967295, 4294967295, 32; |
| %store/vec4 v0x555ec0737d20_0, 0, 32; |
| %load/vec4 v0x555ec0737a00_0; |
| %nor/r; |
| %pushi/vec4 1, 0, 1; |
| %and; |
| %flag_set/vec4 8; |
| %jmp/0xz T_7.2, 8; |
| %load/vec4 v0x555ec0737500_0; |
| %pad/u 11; |
| %ix/vec4 4; |
| %load/vec4a v0x555ec0737e00, 4; |
| %vpi_call 3 77 "$display", $time, " Reading %m addr1=%b dout1=%b", v0x555ec0737500_0, S<0,vec4,u32> {1 0 0}; |
| T_7.2 ; |
| %jmp T_7; |
| .thread T_7; |
| .scope S_0x555ec0736460; |
| T_8 ; |
| %wait E_0x555ec06eeb20; |
| %fork t_7, S_0x555ec0737060; |
| %jmp t_6; |
| .scope S_0x555ec0737060; |
| t_7 ; |
| %load/vec4 v0x555ec0737880_0; |
| %nor/r; |
| %load/vec4 v0x555ec0737f60_0; |
| %nor/r; |
| %and; |
| %flag_set/vec4 8; |
| %jmp/0xz T_8.0, 8; |
| %load/vec4 v0x555ec0738200_0; |
| %parti/s 1, 0, 2; |
| %flag_set/vec4 8; |
| %jmp/0xz T_8.2, 8; |
| %load/vec4 v0x555ec0737b80_0; |
| %parti/s 8, 0, 2; |
| %load/vec4 v0x555ec0737330_0; |
| %pad/u 11; |
| %ix/vec4 4; |
| %flag_mov 8, 4; |
| %ix/load 5, 0, 0; |
| %flag_set/imm 4, 0; |
| %flag_or 4, 8; |
| %store/vec4a v0x555ec0737e00, 4, 5; |
| T_8.2 ; |
| %load/vec4 v0x555ec0738200_0; |
| %parti/s 1, 1, 2; |
| %flag_set/vec4 8; |
| %jmp/0xz T_8.4, 8; |
| %load/vec4 v0x555ec0737b80_0; |
| %parti/s 8, 8, 5; |
| %load/vec4 v0x555ec0737330_0; |
| %pad/u 11; |
| %ix/vec4 4; |
| %flag_mov 8, 4; |
| %ix/load 5, 8, 0; |
| %flag_set/imm 4, 0; |
| %flag_or 4, 8; |
| %store/vec4a v0x555ec0737e00, 4, 5; |
| T_8.4 ; |
| %load/vec4 v0x555ec0738200_0; |
| %parti/s 1, 2, 3; |
| %flag_set/vec4 8; |
| %jmp/0xz T_8.6, 8; |
| %load/vec4 v0x555ec0737b80_0; |
| %parti/s 8, 16, 6; |
| %load/vec4 v0x555ec0737330_0; |
| %pad/u 11; |
| %ix/vec4 4; |
| %flag_mov 8, 4; |
| %ix/load 5, 16, 0; |
| %flag_set/imm 4, 0; |
| %flag_or 4, 8; |
| %store/vec4a v0x555ec0737e00, 4, 5; |
| T_8.6 ; |
| %load/vec4 v0x555ec0738200_0; |
| %parti/s 1, 3, 3; |
| %flag_set/vec4 8; |
| %jmp/0xz T_8.8, 8; |
| %load/vec4 v0x555ec0737b80_0; |
| %parti/s 8, 24, 6; |
| %load/vec4 v0x555ec0737330_0; |
| %pad/u 11; |
| %ix/vec4 4; |
| %flag_mov 8, 4; |
| %ix/load 5, 24, 0; |
| %flag_set/imm 4, 0; |
| %flag_or 4, 8; |
| %store/vec4a v0x555ec0737e00, 4, 5; |
| T_8.8 ; |
| T_8.0 ; |
| %end; |
| .scope S_0x555ec0736460; |
| t_6 %join; |
| %jmp T_8; |
| .thread T_8; |
| .scope S_0x555ec0736460; |
| T_9 ; |
| %wait E_0x555ec06eeb20; |
| %fork t_9, S_0x555ec0736c60; |
| %jmp t_8; |
| .scope S_0x555ec0736c60; |
| t_9 ; |
| %load/vec4 v0x555ec0737880_0; |
| %nor/r; |
| %load/vec4 v0x555ec0737f60_0; |
| %and; |
| %flag_set/vec4 8; |
| %jmp/0xz T_9.0, 8; |
| %load/vec4 v0x555ec0737330_0; |
| %pad/u 11; |
| %ix/vec4 4; |
| %load/vec4a v0x555ec0737e00, 4; |
| %assign/vec4 v0x555ec0737c40_0, 3; |
| T_9.0 ; |
| %end; |
| .scope S_0x555ec0736460; |
| t_8 %join; |
| %jmp T_9; |
| .thread T_9; |
| .scope S_0x555ec0736460; |
| T_10 ; |
| %wait E_0x555ec06eeb20; |
| %fork t_11, S_0x555ec0736e60; |
| %jmp t_10; |
| .scope S_0x555ec0736e60; |
| t_11 ; |
| %load/vec4 v0x555ec0737a00_0; |
| %nor/r; |
| %flag_set/vec4 8; |
| %jmp/0xz T_10.0, 8; |
| %load/vec4 v0x555ec0737500_0; |
| %pad/u 11; |
| %ix/vec4 4; |
| %load/vec4a v0x555ec0737e00, 4; |
| %assign/vec4 v0x555ec0737d20_0, 3; |
| T_10.0 ; |
| %end; |
| .scope S_0x555ec0736460; |
| t_10 %join; |
| %jmp T_10; |
| .thread T_10; |
| # The file index is used to find the file name in the following table. |
| :file_names 4; |
| "N/A"; |
| "<interactive>"; |
| "SRAMWrapper.v"; |
| "sky130_sram_2kbyte_1rw1r_32x512_8_2.v"; |
