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  1. f6fa9e1 final gds oasis by Jeff DiCorpo · 9 months ago main
  2. ca1707a Tapeout! by Piotro · 11 months ago
  3. 6216618 Add tests! by Piotro · 11 months ago
  4. 0852199 Add ppcpu as normal dir by Piotro · 11 months ago
  5. 4592fc3 Initial generated by Piotro · 11 months ago


Submission of pipelined pcpu to openMPW shuttle.

Edition: MPW-8

About ppcpu

ppcpu is a 16-bit RISC processor, with designed from scratch architecture. This is 3rd(.1) revision of processor, which started as little project back in 2020.

This is version 2.2 of ppcpu with many improvements and two cores.


  • Outside bus interface for memory and devices
  • 2 cores
  • Instruction and data caches
  • Custom PCPU ISA
  • Memory paging
  • 4 stage pipeline
  • Microcontroller mode with intergrated memory


Boot tests are is included in verilog/dv/. See README in this directory for description of testbenches

Rest of tests for cpu and ISA are included in ppcpu repo.


For ISA docs see pcpu and ppcpu repositories.


See LICENSE file