|author||Jeff DiCorpo <email@example.com>||Fri Mar 24 09:24:03 2023 -0700|
|committer||Jeff DiCorpo <firstname.lastname@example.org>||Fri Mar 24 09:24:03 2023 -0700|
final gds oasis
Submission of pipelined pcpu to openMPW shuttle.
ppcpu is a 16-bit RISC processor, with designed from scratch architecture. This is 3rd(.1) revision of processor, which started as little project back in 2020.
This is version 2.2 of ppcpu with many improvements and two cores.
Boot tests are is included in
verilog/dv/. See README in this directory for description of testbenches
Rest of tests for cpu and ISA are included in
For ISA docs see