| commit | ca1707ada6ca235f36ac0fdefc619674782d6476 | [log] [tgz] |
|---|---|---|
| author | Piotro <piotro888@wp.pl> | Sat Dec 31 11:23:59 2022 +0100 |
| committer | Piotro <piotro888@wp.pl> | Sat Dec 31 17:01:27 2022 +0100 |
| tree | 9736f9b03717683a6fe15b0fd1d8c819f456740d | |
| parent | 6216618ee5518193ccba05c8cea5261fc3ccdd2e [diff] |
Tapeout! Squashed: Full core sync Switched sram to int_ram (too dificult to integrate, drc) GL tests not passing :c Fix GL tests(.v)!!! and add reduced tb README and license Tapeout! Core resynth after fixes Clean
Submission of pipelined pcpu to openMPW shuttle.
Edition: MPW-8
ppcpu is a 16-bit RISC processor, with designed from scratch architecture. This is 3rd(.1) revision of processor, which started as little project back in 2020.
This is version 2.2 of ppcpu with many improvements and two cores.
Boot tests are is included in verilog/dv/. See README in this directory for description of testbenches
Rest of tests for cpu and ISA are included in ppcpu repo.
For ISA docs see pcpu and ppcpu repositories.
See LICENSE file