lib/core/runs/22_12_26_18_52/config_in.tcl

set ::env(PDK) {sky130A}
set ::env(PDKPATH) {/home/piotro/opt/silicon/pdks/sky130A}
set ::env(STD_CELL_LIBRARY) {sky130_fd_sc_hd}
set ::env(SCLPATH) {/home/piotro/opt/silicon/pdks/sky130A/sky130_fd_sc_hd}
set ::env(DESIGN_DIR) {/home/piotro/caravel_user_project/openlane/core}
set ::env(DESIGN_NAME) {core}
set ::env(DESIGN_IS_CORE) {0}
set ::env(VERILOG_FILES) {/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/defines.v /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/core.v /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu_mul_div.v /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/alu.v /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/decode.v /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/execute.v /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/fetch.v /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/memwb.v /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/pc.v /home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/core/rf.v}
set ::env(VERILOG_INCLUDE_DIRS) {/home/piotro/caravel_user_project/openlane/core/../../verilog/rtl/ppcpu/rtl/}
set ::env(CLOCK_PERIOD) {10}
set ::env(CLOCK_PORT) {i_clk}
set ::env(CLOCK_NET) {i_clk}
set ::env(FP_SIZING) {absolute}
set ::env(DIE_AREA) {0 0 500 500}
set ::env(FP_PIN_ORDER_CFG) {/home/piotro/caravel_user_project/openlane/core/pin_order.cfg}
set ::env(PL_BASIC_PLACEMENT) {0}
set ::env(PL_TARGET_DENSITY) {0.26}
set ::env(VDD_NETS) {vccd1}
set ::env(GND_NETS) {vssd1}
set ::env(DIODE_INSERTION_STRATEGY) {4}
set ::env(RUN_CVC) {1}
set ::env(FP_CORE_UTIL) {45}
set ::env(RT_MAX_LAYER) {met4}
set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) {0.5}
set ::env(ROUTING_CORES) {6}